diff options
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/AsyncResetSpec.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 10 |
3 files changed, 13 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index f9787a48..fdfda3e6 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -7,7 +7,7 @@ import java.io.Writer import scala.collection.mutable import firrtl.ir._ import firrtl.passes._ -import firrtl.transforms.LegalizeAndReductionsTransform +import firrtl.transforms.{FixAddingNegativeLiterals, LegalizeAndReductionsTransform} import firrtl.annotations._ import firrtl.traversals.Foreachers._ import firrtl.PrimOps._ @@ -286,6 +286,7 @@ class VerilogEmitter extends SeqTransform with Emitter { case SIntLiteral(value, IntWidth(width)) => val stringLiteral = value.toString(16) w write (stringLiteral.head match { + case '-' if value == FixAddingNegativeLiterals.minNegValue(width) => s"$width'sh${stringLiteral.tail}" case '-' => s"-$width'sh${stringLiteral.tail}" case _ => s"$width'sh${stringLiteral}" }) diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala index 29c09787..65c68b27 100644 --- a/src/test/scala/firrtlTests/AsyncResetSpec.scala +++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala @@ -278,7 +278,7 @@ class AsyncResetSpec extends FirrtlFlatSpec { |z <= r""".stripMargin ) fixedResult should containLine ("always @(posedge clock or posedge reset) begin") - fixedResult should containLine ("r <= -2'sh2;") + fixedResult should containLine ("r <= 2'sh2;") val intervalResult = compileBody(s""" |input clock : Clock diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 32303949..131f9466 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1604,4 +1604,14 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec { | out <= head_temp""".stripMargin firrtlEquivalenceTest(input, transforms) } + + "addition of negative literals" should "be propagated" in { + val input = + s"""circuit AddTester : + | module AddTester : + | output ref : SInt<2> + | ref <= add(SInt<1>("h-1"), SInt<1>("h-1")) + |""".stripMargin + firrtlEquivalenceTest(input, transforms) + } } |