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-rw-r--r--in.yaml9
-rw-r--r--src/main/scala/firrtl/passes/memlib/DecorateMems.scala16
-rw-r--r--src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala14
-rw-r--r--src/main/scala/firrtl/passes/wiring/Wiring.scala18
-rw-r--r--src/main/scala/firrtl/passes/wiring/WiringTransform.scala43
-rw-r--r--src/test/scala/firrtlTests/WiringTests.scala42
6 files changed, 71 insertions, 71 deletions
diff --git a/in.yaml b/in.yaml
deleted file mode 100644
index f77e0a72..00000000
--- a/in.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
----
-pin:
- name: mypin
-source:
- name: cmd
- module: Htif
-top:
- name: Top
----
diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
index c706a3d9..d73fbc91 100644
--- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
+++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
@@ -15,15 +15,13 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform
case None => state
case Some(r) =>
import CustomYAMLProtocol._
- r.parse[Config] match {
- case Seq(config) =>
- val cN = CircuitName(state.circuit.main)
- val top = TopAnnotation(ModuleName(config.top.name, cN))
- val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)))
- val pin = PinAnnotation(cN, config.pin.name)
- state.copy(annotations = Some(AnnotationMap(Seq(top, source, pin))))
- case Nil => state
- case _ => error("Can only have one config in yaml file")
+ val configs = r.parse[Config]
+ val cN = CircuitName(state.circuit.main)
+ val (as, pins) = configs.foldLeft((Seq.empty[Annotation], Seq.empty[String])) { case ((annos, pins), config) =>
+ val top = TopAnnotation(ModuleName(config.top.name, cN), config.pin.name)
+ val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), config.pin.name)
+ (annos ++ Seq(top, source), pins :+ config.pin.name)
}
+ state.copy(annotations = Some(AnnotationMap(as :+ PinAnnotation(cN, pins.toSeq))))
}
}
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index 8d2c7200..30196fad 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -16,7 +16,7 @@ import wiring._
/** Annotates the name of the pin to add for WiringTransform
*/
-case class PinAnnotation(target: CircuitName, pin: String) extends Annotation with Loose with Unstable {
+case class PinAnnotation(target: CircuitName, pins: Seq[String]) extends Annotation with Loose with Unstable {
def transform = classOf[ReplaceMemMacros]
def duplicate(n: Named) = n match {
case n: CircuitName => this.copy(target = n)
@@ -218,15 +218,19 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform {
val modules = c.modules map updateMemMods(namespace, nameMap, memMods)
// print conf
writer.serialize()
- val pin = getMyAnnotations(state) match {
- case Nil => "pin"
+ val pins = getMyAnnotations(state) match {
+ case Nil => Nil
case Seq(p) => p match {
- case PinAnnotation(c, pin) => pin
+ case PinAnnotation(c, pins) => pins
case _ => error(s"Bad Annotation: ${p}")
}
case _ => throwInternalError
}
- val annos = memMods.collect { case m: ExtModule => SinkAnnotation(ModuleName(m.name, CircuitName(c.main)), pin) }
+ val annos = pins.foldLeft(Seq[Annotation]()) { (seq, pin) =>
+ seq ++ memMods.collect {
+ case m: ExtModule => SinkAnnotation(ModuleName(m.name, CircuitName(c.main)), pin)
+ }
+ }
CircuitState(c.copy(modules = modules ++ memMods), inputForm, Some(AnnotationMap(annos)))
}
}
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index bc1a2524..1ced07eb 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -13,10 +13,13 @@ import WiringUtils._
case class WiringException(msg: String) extends PassException(msg)
-case class WiringInfo(source: String, comp: String, sinks: Map[String, String], top: String)
+case class WiringInfo(source: String, comp: String, sinks: Set[String], pin: String, top: String)
-class Wiring(wi: WiringInfo) extends Pass {
+class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
def name = this.getClass.getSimpleName
+ def run(c: Circuit): Circuit = {
+ wiSeq.foldLeft(c) { (circuit, wi) => wire(circuit, wi) }
+ }
/** Add pins to modules and wires a signal to them, under the scope of a specified top module
* Description:
@@ -30,11 +33,12 @@ class Wiring(wi: WiringInfo) extends Pass {
* Notes:
* - No module uniquification occurs (due to imposed restrictions)
*/
- def run(c: Circuit): Circuit = {
+ def wire(c: Circuit, wi: WiringInfo): Circuit = {
// Split out WiringInfo
val source = wi.source
- val sinks = wi.sinks.keys.toSet
+ val sinks = wi.sinks
val compName = wi.comp
+ val pin = wi.pin
// Maps modules to children instances, i.e. (instance, module)
val childrenMap = getChildrenMap(c)
@@ -55,10 +59,8 @@ class Wiring(wi: WiringInfo) extends Pass {
val portNames = c.modules.foldLeft(Map.empty[String, String]) { (map, m) =>
map + (m.name -> {
val ns = Namespace(m)
- wi.sinks.get(m.name) match {
- case Some(pin) => ns.newName(pin)
- case None => ns.newName(tokenize(compName) filterNot ("[]." contains _) mkString "_")
- }
+ if(sinks.contains(m.name)) ns.newName(pin)
+ else ns.newName(tokenize(compName) filterNot ("[]." contains _) mkString "_")
})
}
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index 7a6fcc65..5c251d6d 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -13,7 +13,7 @@ import WiringUtils._
/** A component, e.g. register etc. Must be declared only once under the TopAnnotation
*/
-case class SourceAnnotation(target: ComponentName) extends Annotation with Loose with Unstable {
+case class SourceAnnotation(target: ComponentName, pin: String) extends Annotation with Loose with Unstable {
def transform = classOf[WiringTransform]
def duplicate(n: Named) = n match {
case n: ComponentName => this.copy(target = n)
@@ -34,7 +34,7 @@ case class SinkAnnotation(target: ModuleName, pin: String) extends Annotation wi
/** A module under which all sink module must be declared, and there is only
* one source component
*/
-case class TopAnnotation(target: ModuleName) extends Annotation with Loose with Unstable {
+case class TopAnnotation(target: ModuleName, pin: String) extends Annotation with Loose with Unstable {
def transform = classOf[WiringTransform]
def duplicate(n: Named) = n match {
case n: ModuleName => this.copy(target = n)
@@ -57,30 +57,35 @@ case class TopAnnotation(target: ModuleName) extends Annotation with Loose with
class WiringTransform extends Transform with SimpleRun {
def inputForm = MidForm
def outputForm = MidForm
- def passSeq(wi: WiringInfo) =
- Seq(new Wiring(wi),
+ def passSeq(wis: Seq[WiringInfo]) =
+ Seq(new Wiring(wis),
InferTypes,
ResolveKinds,
ResolveGenders)
def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
case Nil => CircuitState(state.circuit, state.form)
- case p =>
- val sinks = mutable.HashMap[String, String]()
- val sources = mutable.Set[String]()
- val tops = mutable.Set[String]()
- val comp = mutable.Set[String]()
- p.foreach {
- case SinkAnnotation(m, pin) => sinks(m.name) = pin
- case SourceAnnotation(c) =>
- sources += c.module.name
- comp += c.name
- case TopAnnotation(m) => tops += m.name
+ case p =>
+ // Pin to value
+ val sinks = mutable.HashMap[String, Set[String]]()
+ val sources = mutable.HashMap[String, String]()
+ val tops = mutable.HashMap[String, String]()
+ val comp = mutable.HashMap[String, String]()
+ p.foreach { a =>
+ a match {
+ case SinkAnnotation(m, pin) => sinks(pin) = sinks.getOrElse(pin, Set.empty) + m.name
+ case SourceAnnotation(c, pin) =>
+ sources(pin) = c.module.name
+ comp(pin) = c.name
+ case TopAnnotation(m, pin) => tops(pin) = m.name
+ }
}
(sources.size, tops.size, sinks.size, comp.size) match {
- case (0, 0, p, 0) => state
- case (1, 1, p, 1) if p > 0 =>
- val winfo = WiringInfo(sources.head, comp.head, sinks.toMap, tops.head)
- state.copy(circuit = runPasses(state.circuit, passSeq(winfo)))
+ case (0, 0, p, 0) => state.copy(annotations = None)
+ case (s, t, p, c) if (p > 0) & (s == t) & (t == c) =>
+ val wis = tops.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, top)) =>
+ seq :+ WiringInfo(sources(pin), comp(pin), sinks(pin), pin, top)
+ }
+ state.copy(circuit = runPasses(state.circuit, passSeq(wis)), annotations = None)
case _ => error("Wrong number of sources, tops, or sinks!")
}
}
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 869acd50..b5116f90 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -34,8 +34,8 @@ class WiringTests extends FirrtlFlatSpec {
)
"Wiring from r to X" should "work" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("C", "r", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("C", "r", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -116,14 +116,14 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
(parse(retC.serialize).serialize) should be (parse(check).serialize)
}
"Wiring from r.x to X" should "work" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "r.x", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "r.x", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -159,13 +159,13 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
(parse(retC.serialize).serialize) should be (parse(check).serialize)
}
"Wiring from clk to X" should "work" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "clk", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "clk", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -199,13 +199,13 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
(parse(retC.serialize).serialize) should be (parse(check).serialize)
}
"Two sources" should "fail" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "clk", sinks, "Top")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "clk", sinks, "pin", "Top")
val input =
"""circuit Top :
| module Top :
@@ -225,13 +225,13 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
}
}
"Wiring from A.clk to X, with 2 A's, and A as top" should "work" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "clk", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "clk", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -269,13 +269,13 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
(parse(retC.serialize).serialize) should be (parse(check).serialize)
}
"Wiring from A.clk to X, with 2 A's, and A as top, but Top instantiates X" should "error" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "clk", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "clk", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -297,13 +297,13 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
}
}
"Wiring from A.r[a] to X" should "work" in {
- val sinks = Map(("X"-> "pin"))
- val sas = WiringInfo("A", "r[a]", sinks, "A")
+ val sinks = Set("X")
+ val sas = WiringInfo("A", "r[a]", sinks, "pin", "A")
val input =
"""circuit Top :
| module Top :
@@ -341,7 +341,7 @@ class WiringTests extends FirrtlFlatSpec {
val c = passes.foldLeft(parse(input)) {
(c: Circuit, p: Pass) => p.run(c)
}
- val wiringPass = new Wiring(sas)
+ val wiringPass = new Wiring(Seq(sas))
val retC = wiringPass.run(c)
(parse(retC.serialize).serialize) should be (parse(check).serialize)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:37:23 +0000