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-rw-r--r--Makefile3
-rw-r--r--TODO2
-rw-r--r--src/main/stanza/errors.stanza8
-rw-r--r--src/main/stanza/firrtl-ir.stanza2
-rw-r--r--src/main/stanza/flo.stanza2
-rw-r--r--src/main/stanza/ir-parser.stanza2
-rw-r--r--src/main/stanza/ir-utils.stanza2
-rw-r--r--src/main/stanza/passes.stanza4
-rw-r--r--src/main/stanza/primop.stanza4
-rw-r--r--src/main/stanza/verilog.stanza7
-rw-r--r--test/passes/expand-connect-indexed/bundle-vecs.fir6
-rw-r--r--test/passes/infer-types/primops.fir20
12 files changed, 49 insertions, 13 deletions
diff --git a/Makefile b/Makefile
index b46d2cb8..c5951281 100644
--- a/Makefile
+++ b/Makefile
@@ -39,6 +39,9 @@ errors:
chisel3:
cd $(test_dir)/chisel3 && lit -v . --path=$(root_dir)/utils/bin/
+refchip:
+ cd $(test_dir)/refchip && lit -v . --path=$(root_dir)/utils/bin/
+
features:
cd $(test_dir)/features && lit -v . --path=$(root_dir)/utils/bin/
diff --git a/TODO b/TODO
index e91c536a..56007996 100644
--- a/TODO
+++ b/TODO
@@ -5,10 +5,10 @@
======== Current Tasks ========
add include support
change parser to accept subword, but error
---Merge with master
put clocks on accessors
add clock check to high firrtl check
registers in onreset cannot have flips
+add equivalence to spec
Tests:
Lowering for instance types with bundle ports
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 6cdd1dca..f0eb5a70 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -218,6 +218,8 @@ defn check-high-form-primop (e:DoPrim, errors:Vector<PassException>,info:FileInf
GREATER-EQ-OP : correct-num(2,0)
EQUAL-OP : correct-num(2,0)
NEQUAL-OP : correct-num(2,0)
+ EQUIV-OP : correct-num(2,0)
+ NEQUIV-OP : correct-num(2,0)
MUX-OP : correct-num(3,0)
PAD-OP : correct-num(1,1)
AS-UINT-OP : correct-num(1,0)
@@ -568,8 +570,10 @@ defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -
LESS-EQ-OP : false
GREATER-OP : false
GREATER-EQ-OP : false
- EQUAL-OP : all-same-type(args(e))
- NEQUAL-OP : all-same-type(args(e))
+ EQUAL-OP : false
+ NEQUAL-OP : false
+ EQUIV-OP : all-same-type(args(e))
+ NEQUIV-OP : all-same-type(args(e))
MUX-OP :
all-same-type(tail(args(e)))
is-uint(head(args(e)))
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 822b8610..8de688d7 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -50,6 +50,8 @@ public val GREATER-OP = new PrimOp
public val GREATER-EQ-OP = new PrimOp
public val NEQUAL-OP = new PrimOp
public val EQUAL-OP = new PrimOp
+public val NEQUIV-OP = new PrimOp
+public val EQUIV-OP = new PrimOp
public val MUX-OP = new PrimOp
public val PAD-OP = new PrimOp
public val AS-UINT-OP = new PrimOp
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index a7b726a7..f6e75383 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -38,6 +38,8 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
LESS-EQ-OP : "lte" ;; todo: swap args
GREATER-OP : "lt" ;; todo: swap args
GREATER-EQ-OP : "lte" ;; todo: signed version
+ NEQUIV-OP : "neq"
+ EQUIV-OP : "eq"
NEQUAL-OP : "neq"
EQUAL-OP : "eq"
MUX-OP : "mux"
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 9d9893c5..34d9ef57 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -56,6 +56,8 @@ OPERATORS[`gt] = GREATER-OP
OPERATORS[`geq] = GREATER-EQ-OP
OPERATORS[`eq] = EQUAL-OP
OPERATORS[`neq] = NEQUAL-OP
+OPERATORS[`eqv] = EQUIV-OP
+OPERATORS[`neqv] = NEQUIV-OP
OPERATORS[`mux] = MUX-OP
OPERATORS[`pad] = PAD-OP
OPERATORS[`neg] = NEG-OP
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 93dc0d79..6e34a1e5 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -139,6 +139,8 @@ defmethod print (o:OutputStream, op:PrimOp) :
LESS-EQ-OP : "leq"
GREATER-OP : "gt"
GREATER-EQ-OP : "geq"
+ EQUIV-OP : "eqv"
+ NEQUIV-OP : "neqv"
EQUAL-OP : "eq"
NEQUAL-OP : "neq"
MUX-OP : "mux"
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 36cc2c46..6ac2cfeb 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1134,7 +1134,7 @@ public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexe
defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
defn equality (e1:Expression,e2:Expression) -> Expression :
- DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
+ DoPrim(EQUIV-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
defn get-name (e:Expression) -> Symbol :
match(e) :
(e:WRef) : symbol-join([name(e) temp-delin])
@@ -1254,7 +1254,7 @@ defn OR (e1:Expression,e2:Expression) -> Expression :
defn NOT (e1:Expression) -> Expression :
if e1 == one : zero
else if e1 == zero : one
- else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1)))
+ else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(IntWidth(1)))
defn children (e:Expression) -> List<Expression> :
val es = Vector<Expression>()
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index 0e343d74..f7eb6d04 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -39,6 +39,8 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim :
GREATER-EQ-OP : DoPrim(GREATER-EQ-OP,args(e),consts(e),u())
EQUAL-OP : DoPrim(EQUAL-OP,args(e),consts(e),u())
NEQUAL-OP : DoPrim(NEQUAL-OP,args(e),consts(e),u())
+ EQUIV-OP : DoPrim(EQUIV-OP,args(e),consts(e),u())
+ NEQUIV-OP : DoPrim(NEQUIV-OP,args(e),consts(e),u())
MUX-OP : DoPrim(MUX-OP,args(e),consts(e),of-type(args(e)[1]))
PAD-OP : DoPrim(PAD-OP,args(e),consts(e),of-type(args(e)[0]))
AS-UINT-OP : DoPrim(AS-UINT-OP,args(e),consts(e),u())
@@ -98,6 +100,8 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
GREATER-EQ-OP : IntWidth(1)
EQUAL-OP : IntWidth(1)
NEQUAL-OP : IntWidth(1)
+ EQUIV-OP : IntWidth(1)
+ NEQUIV-OP : IntWidth(1)
MUX-OP :
add(v,WGeq(IntWidth(1),width!(args(e)[0])))
add(v,WGeq(width!(args(e)[0]),IntWidth(1)))
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index ca47170b..d8810622 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -60,7 +60,10 @@ defn emit-signed-if-any (e:Expression,ls:List<Expression>) -> String :
for x in ls do :
if type(x) typeof SIntType : signed? = true
if not signed? : emit(e)
- else : string-join(["$signed(" emit(e) ")"])
+ else :
+ match(type(e)) :
+ (t:SIntType) : string-join(["$signed(" emit(e) ")"])
+ (t:UIntType) : string-join(["$signed({1'b0," emit(e) "})"])
defn emit (e:Expression) -> String :
match(e) :
@@ -92,6 +95,8 @@ defn emit (e:Expression) -> String :
LESS-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " <= " emit-signed-if-any(args(e)[1],args(e))]
GREATER-OP : [emit-signed-if-any(args(e)[0],args(e)) " > " emit-signed-if-any(args(e)[1],args(e))]
GREATER-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " >= " emit-signed-if-any(args(e)[1],args(e))]
+ NEQUIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))]
+ EQUIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))]
NEQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))]
EQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))]
MUX-OP :
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 325c0fcb..bc1b6892 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -24,10 +24,10 @@ circuit top :
; CHECK: wire b{{[_$]+}}y : UInt<32>
; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
; CHECK: node i!0 = i
- ; CHECK: when eq(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x
+ ; CHECK: when eqv(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x
; CHECK: node i!1 = i
- ; CHECK: when eq(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y
- ; CHECK: when eq(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y
+ ; CHECK: when eqv(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y
+ ; CHECK: when eqv(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y
j := b.x
b.y := UInt(1)
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 61656e9c..8e5afb1b 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -87,13 +87,25 @@ circuit top :
node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
- node vneq = neq(a, b) ;CHECK: node vneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node veq = eq(a, c) ;CHECK: node veq = eq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+ node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node xeq = eq(a, d) ;CHECK: node xeq = eq(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
+ node yeq = eq(c, b) ;CHECK: node yeq = eq(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
+ node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+
+ node vneq = neq(a, c) ;CHECK: node vneq = neq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node xneq = neq(a, d) ;CHECK: node xneq = neq(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
+ node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
- node veq = eq(a, b) ;CHECK: node veq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
- node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
- node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+ node vneqv = neqv(a, b) ;CHECK: node vneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node wneqv = neqv(a, b) ;CHECK: node wneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node zneqv = neqv(c, d) ;CHECK: node zneqv = neqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+
+ node veqv = eqv(a, b) ;CHECK: node veqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node weqv = eqv(a, b) ;CHECK: node weqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+ node zeqv = eqv(c, d) ;CHECK: node zeqv = eqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 13:44:28 +0000