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-rw-r--r--src/main/scala/firrtl/DebugUtils.scala63
-rw-r--r--src/main/scala/firrtl/Logger.scala59
-rw-r--r--src/main/scala/firrtl/Test.scala32
-rw-r--r--src/main/scala/firrtl/Utils.scala2
-rw-r--r--test/parser/bundle.fir26
-rw-r--r--test/parser/gcd.fir2
6 files changed, 106 insertions, 78 deletions
diff --git a/src/main/scala/firrtl/DebugUtils.scala b/src/main/scala/firrtl/DebugUtils.scala
new file mode 100644
index 00000000..80c0d240
--- /dev/null
+++ b/src/main/scala/firrtl/DebugUtils.scala
@@ -0,0 +1,63 @@
+// Private implicit classes and other utility functions for debugging
+
+package firrtl
+
+import java.io.PrintWriter
+import Utils._
+
+private object DebugUtils {
+
+
+ /** Private class for recording and organizing debug information */
+ class Logger private (
+ writer: PrintWriter,
+ printMode: Symbol,
+ printVars: List[Symbol]){
+
+ // Legal printModes: 'none, 'error, 'warn, 'info, 'debug, 'trace
+ require(List('none, 'error, 'warn, 'info, 'debug, 'trace) contains printMode)
+ val errorEnable = List('error, 'warn, 'info, 'debug, 'trace) contains printMode
+ val warnEnable = List('warn, 'info, 'debug, 'trace) contains printMode
+ val infoEnable = List('info, 'debug, 'trace) contains printMode
+ val debugEnable = List('debug, 'trace) contains printMode
+ val traceEnable = List('trace) contains printMode
+ val circuitEnable = printVars contains 'circuit
+ val debugFlags = printVars.map(_ -> true).toMap.withDefaultValue(false)
+
+ def error(message: => String){
+ if (errorEnable) writer.println(message.split("\n").map("[error] " + _).mkString("\n"))
+ }
+ def warn(message: => String){
+ if (warnEnable) writer.println(message.split("\n").map("[warn] " + _).mkString("\n"))
+ }
+ def info(message: => String){
+ if (infoEnable) writer.println(message.split("\n").map("[info] " + _).mkString("\n"))
+ }
+ def debug(message: => String){
+ if (debugEnable) writer.println(message.split("\n").map("[debug] " + _).mkString("\n"))
+ }
+ def trace(message: => String){
+ if (traceEnable) writer.println(message.split("\n").map("[trace] " + _).mkString("\n"))
+ }
+ def printDebug(circuit: Circuit){
+ if (circuitEnable) this.debug(circuit.serialize(debugFlags))
+ }
+ // Used if not autoflushing
+ def flush() = writer.flush()
+
+ }
+ /** Factory object for logger
+ *
+ * Logger records and organizes debug information
+ */
+ object Logger
+ {
+ def apply(writer: PrintWriter): Logger =
+ new Logger(writer, 'warn, List())
+ def apply(writer: PrintWriter, printMode: Symbol): Logger =
+ new Logger(writer, printMode, List())
+ def apply(writer: PrintWriter, printMode: Symbol, printVars: List[Symbol]): Logger =
+ new Logger(writer, printMode, printVars)
+ def apply(): Logger = new Logger(null, 'none, List())
+ }
+}
diff --git a/src/main/scala/firrtl/Logger.scala b/src/main/scala/firrtl/Logger.scala
deleted file mode 100644
index 85969307..00000000
--- a/src/main/scala/firrtl/Logger.scala
+++ /dev/null
@@ -1,59 +0,0 @@
-package firrtl
-
-import java.io.PrintWriter
-import Utils._
-
-class Logger private (
- writer: PrintWriter,
- printMode: Symbol,
- printVars: List[Symbol]){
-
- // Legal printModes: 'none, 'error, 'warn, 'info, 'debug, 'trace
- require(List('none, 'error, 'warn, 'info, 'debug, 'trace) contains printMode)
- val errorEnable = List('error, 'warn, 'info, 'debug, 'trace) contains printMode
- val warnEnable = List('warn, 'info, 'debug, 'trace) contains printMode
- val infoEnable = List('info, 'debug, 'trace) contains printMode
- val debugEnable = List('debug, 'trace) contains printMode
- val traceEnable = List('trace) contains printMode
- val circuitEnable = printVars contains 'circuit
- val debugFlags = printVars.map(_ -> true).toMap.withDefaultValue(false)
-
- def error(message: => String){
- if (errorEnable) writer.println(message.split("\n").map("[error] " + _).mkString("\n"))
- }
- def warn(message: => String){
- if (warnEnable) writer.println(message.split("\n").map("[warn] " + _).mkString("\n"))
- }
- def info(message: => String){
- if (infoEnable) writer.println(message.split("\n").map("[info] " + _).mkString("\n"))
- }
- def debug(message: => String){
- if (debugEnable) writer.println(message.split("\n").map("[debug] " + _).mkString("\n"))
- }
- def trace(message: => String){
- if (traceEnable) writer.println(message.split("\n").map("[trace] " + _).mkString("\n"))
- }
-
- def printType(node: => AST){
- val tpe = node.getType
- if( tpe.nonEmpty ) this.debug(s"@<t:${tpe.get.serialize}>")
- }
-
- def printDebug(circuit: Circuit){
- if (circuitEnable) this.debug(circuit.serialize(debugFlags))
- }
- // Used if not autoflushing
- def flush() = writer.flush()
-
-}
-
-object Logger
-{
- def apply(writer: PrintWriter): Logger =
- new Logger(writer, 'warn, List())
- def apply(writer: PrintWriter, printMode: Symbol): Logger =
- new Logger(writer, printMode, List())
- def apply(writer: PrintWriter, printMode: Symbol, printVars: List[Symbol]): Logger =
- new Logger(writer, printMode, printVars)
- def apply(): Logger = new Logger(null, 'none, List())
-}
diff --git a/src/main/scala/firrtl/Test.scala b/src/main/scala/firrtl/Test.scala
index b1e45762..86c3616a 100644
--- a/src/main/scala/firrtl/Test.scala
+++ b/src/main/scala/firrtl/Test.scala
@@ -2,6 +2,7 @@ package firrtl
import java.io._
import Utils._
+import DebugUtils._
object Test
{
@@ -11,7 +12,7 @@ object Test
private val defaultOptions = Map[Symbol, Any]().withDefaultValue(false)
// Parse input file and print to output
- private def highFIRRTL(input: String, output: String, logger: Logger)
+ private def highFIRRTL(input: String, output: String)(implicit logger: Logger)
{
val ast = Parser.parse(input)
val writer = new PrintWriter(new File(output))
@@ -19,6 +20,21 @@ object Test
writer.close()
logger.printDebug(ast)
}
+ private def verilog(input: String, output: String)(implicit logger: Logger)
+ {
+ logger.warn("Verilog compiler not fully implemented")
+ val ast = time("parse"){ Parser.parse(input) }
+ // Execute passes
+ //val ast2 = time("inferTypes"){ inferTypes(ast) }
+ val ast2 = ast
+
+ // Output
+ val writer = new PrintWriter(new File(output))
+ var outString = time("serialize"){ ast2.serialize() }
+ writer.write(outString)
+ writer.close()
+ logger.printDebug(ast2)
+ }
def main(args: Array[String])
{
@@ -89,7 +105,7 @@ object Test
}
implicit val logger = options('log) match {
case s: String => Logger(new PrintWriter(new FileOutputStream(s)), debugMode, printVars)
- case false => Logger(new PrintWriter(System.out, true), debugMode, printVars)
+ case false => Logger(new PrintWriter(System.err, true), debugMode, printVars)
}
// -p "printVars" options only print for debugMode > 'debug, warn if -p enabled and debugMode < 'debug
@@ -97,9 +113,17 @@ object Test
logger.warn("-p options will not print unless debugMode (-d) is debug or trace")
options('compiler) match {
- case "Verilog" => throw new Exception("Verilog compiler not currently supported!")
- case "HighFIRRTL" => highFIRRTL(input, output, logger)
+ case "verilog" => verilog(input, output)
+ case "HighFIRRTL" => highFIRRTL(input, output)
case other => throw new Exception("Invalid compiler! " + other)
}
}
+
+ def time[R](str: String)(block: => R)(implicit logger: Logger): R = {
+ val t0 = System.currentTimeMillis()
+ val result = block // call-by-name
+ val t1 = System.currentTimeMillis()
+ logger.info(s"Time to ${str}: ${t1 - t0} ms")
+ result
+ }
}
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index b50bd7b5..8e9889b9 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -32,7 +32,7 @@ object Utils {
implicit class BigIntUtils(bi: BigInt){
def serialize(implicit flags: FlagMap = FlagMap): String =
- "\"h0" + bi.toString(16) + "\""
+ "\"h" + bi.toString(16) + "\""
}
implicit class ASTUtils(ast: AST) {
diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir
index 15fa26d0..c9f5e226 100644
--- a/test/parser/bundle.fir
+++ b/test/parser/bundle.fir
@@ -23,21 +23,21 @@ circuit top :
; CHECK: circuit top :
; CHECK: module top :
; CHECK: wire z : { x : UInt, flip y : SInt }
-; CHECK: z.x := UInt("h01")
-; CHECK: z.y := SInt("h01")
+; CHECK: z.x := UInt("h1")
+; CHECK: z.y := SInt("h1")
; CHECK: node x = z.x
; CHECK: node y = z.y
; CHECK: wire a : UInt<3>[10]
-; CHECK: a[0] := UInt("h01")
-; CHECK: a[1] := UInt("h01")
-; CHECK: a[2] := UInt("h01")
-; CHECK: a[3] := UInt("h01")
-; CHECK: a[4] := UInt("h01")
-; CHECK: a[5] := UInt("h01")
-; CHECK: a[6] := UInt("h01")
-; CHECK: a[7] := UInt("h01")
-; CHECK: a[8] := UInt("h01")
-; CHECK: a[9] := UInt("h01")
+; CHECK: a[0] := UInt("h1")
+; CHECK: a[1] := UInt("h1")
+; CHECK: a[2] := UInt("h1")
+; CHECK: a[3] := UInt("h1")
+; CHECK: a[4] := UInt("h1")
+; CHECK: a[5] := UInt("h1")
+; CHECK: a[6] := UInt("h1")
+; CHECK: a[7] := UInt("h1")
+; CHECK: a[8] := UInt("h1")
+; CHECK: a[9] := UInt("h1")
; CHECK: node b = a[2]
-; CHECK: read accessor c = a[UInt("h03")]
+; CHECK: read accessor c = a[UInt("h3")]
diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir
index 03eb6ba9..3a9317b8 100644
--- a/test/parser/gcd.fir
+++ b/test/parser/gcd.fir
@@ -47,6 +47,6 @@ circuit GCD :
; CHECK: x := a
; CHECK: y := b
; CHECK: z := x
-; CHECK: node T_20 = eq(y, UInt<1>("h00"))
+; CHECK: node T_20 = eq(y, UInt<1>("h0"))
; CHECK: v := T_20
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:37:52 +0000