diff options
| -rw-r--r-- | src/main/scala/firrtl/transforms/CheckCombLoops.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala index b7ba5c5e..53be9a98 100644 --- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala +++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala @@ -279,26 +279,33 @@ class CheckCombLoops extends Transform with RegisteredTransform with PreservesAl val sources = tos.map(to => mt.ref(to.name)) CombinationalPath(sink, sources.toSeq) } - (state.copy(annotations = state.annotations ++ annos), errors, simplifiedModuleGraphs) + (state.copy(annotations = state.annotations ++ annos), errors, simplifiedModuleGraphs, moduleGraphs) } /** * Returns a Map from Module name to port connectivity */ def analyze(state: CircuitState): collection.Map[String,DiGraph[String]] = { - val (result, errors, connectivity) = run(state) + val (result, errors, connectivity, _) = run(state) connectivity.map { case (k, v) => (k, v.transformNodes(ln => ln.name)) } } + /** + * Returns a Map from Module name to complete netlist connectivity + */ + def analyzeFull(state: CircuitState): collection.Map[String,DiGraph[LogicNode]] = { + run(state)._4 + } + def execute(state: CircuitState): CircuitState = { val dontRun = state.annotations.contains(DontCheckCombLoopsAnnotation) if (dontRun) { logger.warn("Skipping Combinational Loop Detection") state } else { - val (result, errors, connectivity) = run(state) + val (result, errors, connectivity, _) = run(state) errors.trigger() result } |