diff options
| -rw-r--r-- | src/main/scala/firrtl/ir/IR.scala | 12 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/InferReadWriteSpec.scala | 22 |
2 files changed, 18 insertions, 16 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala index 76c7c91e..afe28634 100644 --- a/src/main/scala/firrtl/ir/IR.scala +++ b/src/main/scala/firrtl/ir/IR.scala @@ -138,14 +138,14 @@ case class DefMemory( def serialize: String = s"mem $name :" + info.serialize + indent( - Seq("\ndata-type => " + dataType.serialize, + (Seq("\ndata-type => " + dataType.serialize, "depth => " + depth, "read-latency => " + readLatency, - "write-latency => " + writeLatency, - readers map ("reader => " + _), - writers map ("writer => " + _), - readwriters map ("readwriter" + _), - "read-under-write => undefined") mkString "\n") + "write-latency => " + writeLatency) ++ + (readers map ("reader => " + _)) ++ + (writers map ("writer => " + _)) ++ + (readwriters map ("readwriter => " + _)) ++ + Seq("read-under-write => undefined")) mkString "\n") } case class DefNode(info: Info, name: String, value: Expression) extends Statement with IsDeclaration { def serialize: String = s"node $name = ${value.serialize}" + info.serialize diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 93f73741..7e3383b2 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -36,25 +36,24 @@ import Annotations._ class InferReadWriteSpec extends SimpleTransformSpec { object InferReadWriteCheckPass extends Pass { val name = "Check Infer ReadWrite Ports" - var foundReadWrite = false - def findReadWrite(s: Statement): Unit = s match { - case s: DefMemory if s.readLatency > 0 => - foundReadWrite = s.name == "mem" && s.readwriters.size == 1 + def findReadWrite(s: Statement): Boolean = s match { + case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 => + s.name == "mem" && s.readwriters.head == "rw_0" case s: Block => - s.stmts foreach findReadWrite - case _ => + s.stmts exists findReadWrite + case _ => false } def run (c: Circuit) = { val errors = new Errors - c.modules foreach { + val foundReadWrite = c.modules exists { case m: Module => findReadWrite(m.body) - case m: ExtModule => m + case m: ExtModule => false } if (!foundReadWrite) { errors append new PassException("Readwrite ports are not found!") + errors.trigger } - errors.trigger c } } @@ -99,6 +98,9 @@ circuit sram6t : """.stripMargin val annotaitonMap = AnnotationMap(Seq(InferReadWriteAnnotation("sram6t", TransID(-1)))) - compile(parse(input), annotaitonMap, new java.io.StringWriter) + val writer = new java.io.StringWriter + compile(parse(input), annotaitonMap, writer) + // Check correctness of firrtl + parse(writer.toString) } } |