diff options
| -rw-r--r-- | src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 20 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala index 2ba28ebb..d1520eae 100644 --- a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala +++ b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala @@ -17,7 +17,7 @@ object FixAddingNegativeLiterals { * @param width width of the negative number * @return maximum negative number */ - def minNegValue(width: BigInt): BigInt = -(1 << (width.toInt - 1)) + def minNegValue(width: BigInt): BigInt = -(BigInt(1) << (width.toInt - 1)) /** Updates the type of the DoPrim from its arguments (e.g. if is UnknownType) * @param d input DoPrim diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 7001a724..4a3686fa 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -735,6 +735,26 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { result should containLine("assign z = _GEN_0[1:0];") } + it should "correctly emit addition with a negative literal with width > 32" in { + val result = compileBody( + """input x : SInt<34> + |output z : SInt<34> + |z <= asSInt(tail(add(x, SInt<34>(-2)), 1)) + |""".stripMargin + ) + result should containLine("assign z = $signed(x) - 34'sh2;") + } + + it should "correctly emit conjunction with a negative literal with width > 32" in { + val result = compileBody( + """input x : SInt<34> + |output z : SInt<34> + |z <= asSInt(and(x, SInt<34>(-2))) + |""".stripMargin + ) + result should containLine("assign z = $signed(x) & -34'sh2;") + } + it should "emit FileInfo as Verilog comment" in { def result(info: String): CircuitState = compileBody( s"""input x : UInt<2> |