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-rw-r--r--.run_chisel_tests.sh2
-rw-r--r--.travis.yml1
2 files changed, 3 insertions, 0 deletions
diff --git a/.run_chisel_tests.sh b/.run_chisel_tests.sh
index c52bfee1..9d965558 100644
--- a/.run_chisel_tests.sh
+++ b/.run_chisel_tests.sh
@@ -5,6 +5,8 @@ set -e
if git log --format=%B --no-merges ${TRAVIS_COMMIT_RANGE/.../..} | grep '\[skip chisel tests\]'; then
exit 0
else
+ git clone https://github.com/freechipsproject/treadle.git --depth 10
+ (cd treadle && sbt $SBT_ARGS +publishLocal)
git clone https://github.com/ucb-bar/chisel3.git
mkdir -p chisel3/lib
cp utils/bin/firrtl.jar chisel3/lib
diff --git a/.travis.yml b/.travis.yml
index 2837dbba..bb250718 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -78,6 +78,7 @@ jobs:
use: firrtl_build
script:
- verilator --version
+ - sbt $SBT_ARGS +publishLocal
- bash .run_chisel_tests.sh
- stage: test
name: "Formal equivalence: RocketCore"