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-rw-r--r--TODO1
-rw-r--r--src/main/stanza/compilers.stanza7
-rw-r--r--src/main/stanza/custom-compiler.stanza2
-rw-r--r--src/main/stanza/passes.stanza312
-rw-r--r--test/passes/expand-accessors/simple.fir15
-rw-r--r--test/passes/expand-accessors/simple2.fir17
-rw-r--r--test/passes/inline-indexers/bundle-vecs.fir (renamed from test/passes/expand-connect-indexed/bundle-vecs.fir)0
-rw-r--r--test/passes/inline-indexers/init-vecs.fir (renamed from test/passes/expand-connect-indexed/init-vecs.fir)0
-rw-r--r--test/passes/inline-indexers/simple.fir20
-rw-r--r--test/passes/inline-indexers/simple2.fir26
-rw-r--r--test/passes/inline-indexers/simple3.fir20
-rw-r--r--test/passes/inline-indexers/simple4.fir25
-rw-r--r--test/passes/inline-indexers/simple5.fir21
-rw-r--r--test/passes/inline-indexers/simple6.fir26
14 files changed, 366 insertions, 126 deletions
diff --git a/TODO b/TODO
index 1c85c5f1..b8086632 100644
--- a/TODO
+++ b/TODO
@@ -3,6 +3,7 @@ Support ASIC backend
Mem of vec, should just work?
ASIC rams (pass to replace smem with black box)
Readwrite Port
+Move WorkingIR->RealIR right after width inference, update other passes accordingly
================================================
========== ADAM's BIG ARSE TODO LIST ============
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 1e978a2e..cc72bd14 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -25,7 +25,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
CheckGenders()
ExpandAccessors()
LowerToGround()
- ExpandIndexedConnects()
+ InlineIndexed()
ExpandWhens()
InferWidths()
Pad()
@@ -44,7 +44,7 @@ public defstruct StandardVerilog <: Compiler :
public defmethod passes (c:StandardVerilog) -> List<Pass> :
to-list $ [
RemoveSpecialChars() ;R
- RemoveScopes() ;R
+ ;RemoveScopes() ;R
CheckHighForm() ;R
TempElimination() ;R
ToWorkingIR() ;R -> W
@@ -56,7 +56,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
CheckTypes() ;R
ExpandAccessors() ;W
LowerToGround() ;W
- ExpandIndexedConnects() ;W
+ ;ExpandIndexedConnects() ;W
+ InlineIndexed()
InferTypes() ;R
CheckGenders() ;W
ExpandWhens() ;W
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index 36a6474f..0f43da58 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -28,7 +28,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
CheckGenders()
ExpandAccessors()
LowerToGround()
- ExpandIndexedConnects()
+ InlineIndexed()
InferTypes()
CheckGenders()
ExpandWhens()
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 99fb8172..ae3a30aa 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -21,7 +21,8 @@ public val standard-passes = to-list $ [
CheckGenders()
ExpandAccessors()
LowerToGround()
- ExpandIndexedConnects()
+ ;ExpandIndexedConnects()
+ InlineIndexed()
ExpandWhens()
InferWidths()
Inline()
@@ -67,17 +68,19 @@ public defstruct WIndex <: Expression :
type: Type with: (as-method => true)
gender: Gender with: (as-method => true)
-defstruct ConnectToIndexed <: Stmt :
+defstruct DecFromIndexer <: Stmt :
info: FileInfo with: (as-method => true)
index: Expression
- locs: List<Expression>
- exp: Expression
+ exps: List<Expression>
+ name: Symbol
+ type: Type
-defstruct ConnectFromIndexed <: Stmt :
+defstruct DecToIndexer <: Stmt :
info: FileInfo with: (as-method => true)
index: Expression
- loc: Expression
exps: List<Expression>
+ name: Symbol
+ type: Type
;================ WORKING IR UTILS =========================
@@ -259,12 +262,12 @@ defmethod print (o:OutputStream, e:WIndex) :
print-all(o,[exp(e) "[" value(e) "]"])
print-debug(o,e as ?)
-defmethod print (o:OutputStream, c:ConnectToIndexed) :
- print-all(o, [locs(c) "[" index(c) "] := " exp(c)])
+defmethod print (o:OutputStream, c:DecFromIndexer) :
+ print-all(o, ["indexer " exps(c) "[" index(c) "] = " name(c) " : " type(c)])
print-debug(o,c as ?)
-defmethod print (o:OutputStream, c:ConnectFromIndexed) :
- print-all(o, [loc(c) " := " exps(c) "[" index(c) "]" ])
+defmethod print (o:OutputStream, c:DecToIndexer) :
+ print-all(o, ["indexer " name(c) " = " exps(c) "[" index(c) "] : " type(c)])
print-debug(o,c as ?)
defmethod map (f: Expression -> Expression, e: WSubfield) :
@@ -272,10 +275,10 @@ defmethod map (f: Expression -> Expression, e: WSubfield) :
defmethod map (f: Expression -> Expression, e: WIndex) :
WIndex(f(exp(e)), value(e), type(e), gender(e))
-defmethod map (f: Expression -> Expression, c:ConnectToIndexed) :
- ConnectToIndexed(info(c),f(index(c)), map(f, locs(c)), f(exp(c)))
-defmethod map (f: Expression -> Expression, c:ConnectFromIndexed) :
- ConnectFromIndexed(info(c),f(index(c)), f(loc(c)), map(f, exps(c)))
+defmethod map (f: Expression -> Expression, c:DecFromIndexer) :
+ DecFromIndexer(info(c),f(index(c)), map(f, exps(c)), name(c), type(c))
+defmethod map (f: Expression -> Expression, c:DecToIndexer) :
+ DecToIndexer(info(c),f(index(c)), map(f, exps(c)), name(c), type(c))
defmethod map (f: Type -> Type, e: WRef) :
WRef(name(e), f(type(e)), kind(e), gender(e))
@@ -850,12 +853,12 @@ defn resolve-genders (c:Circuit) :
resolve-genders(m,c)
;;============== EXPAND ACCESSORS ================================
-; This pass expands non-memory accessors into ConnectToIndexed or
+; This pass expands non-memory accessors into DecFromIndexer or
; ConnectFromIndexed. All elements of the vector are
; explicitly written out, then indexed. Depending on the gender
-; of the accessor, it is transformed into ConnectToIndexed (male) or
-; ConnectFromIndexed (female)
-; Eg:
+; of the accessor, it is transformed into DecFromIndexer (male) or
+; DecToIndexer (female)
+
public defstruct ExpandAccessors <: Pass
public defmethod pass (b:ExpandAccessors) -> (Circuit -> Circuit) : expand-accessors
public defmethod name (b:ExpandAccessors) -> String : "Expand Accessors"
@@ -876,18 +879,11 @@ defn expand-stmt (s:Stmt) -> Stmt :
if mem? : s
else :
val vtype = type(type(source(s)) as VectorType)
- val wire = DefWire(info(s),name(s),vtype)
switch {acc-dir(s) == _} :
- READ : Begin{list(wire,_)} $ ConnectFromIndexed(
- info(s),
- index(s),
- WRef(name(wire),vtype,NodeKind(),FEMALE),
- expand-vector(source(s)))
- WRITE : Begin{list(wire,_)} $ ConnectToIndexed(
- info(s),
- index(s),
- expand-vector(source(s)),
- WRef(name(wire),vtype,NodeKind(),MALE))
+ READ : DecToIndexer(info(s),index(s),expand-vector(source(s)),
+ name(s), vtype)
+ WRITE : DecFromIndexer(info(s),index(s),expand-vector(source(s)),
+ name(s), vtype)
INFER : error("Shouldn't be here")
RDWR : error("Haven't implemented RDWR yet")
(s) : map(expand-stmt,s)
@@ -897,8 +893,9 @@ defn expand-accessors (c:Circuit) :
val modules* =
for m in modules(c) map :
match(m) :
- (m:InModule) : InModule(info(m),name(m),ports(m),expand-stmt(body(m)))
(m:ExModule) : m
+ (m:InModule) :
+ InModule(info(m),name(m),ports(m),expand-stmt(body(m)))
;;=============== LOWERING TO GROUND TYPES =============================
; All non-ground (elevated) types (Vectors, Bundles) are expanded out to
@@ -1091,46 +1088,31 @@ defn lower (body:Stmt) -> Stmt :
switch fn ([x,y]) : lgender == x and rgender == y :
[FEMALE,MALE] : Connect(info(s),l*,r*)
[MALE,FEMALE] : Connect(info(s),r*,l*)
- (s:ConnectFromIndexed) : Begin(ls) where :
+ (s:DecToIndexer|DecFromIndexer) : Begin(ls) where :
val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash)
val index* = exp(head $ expand-expr(index(s)))
for e in exps(s) do :
- for (r in expand-expr(e),l in expand-expr(loc(s))) do :
- val n = name(exp(l) as WRef)
+ for (r in expand-expr(e), ntf in generate-entry(name(s),type(s))) do:
+ val n = name(ntf)
val x = get?(ctable,n,Vector<EF>())
add(x,r)
ctable[n] = x
- val ls = for l in expand-expr(loc(s)) map :
- val n = name(exp(l) as WRef)
- val lgender = FEMALE * flip(l)
+ val default-gender = match(s) :
+ (s:DecToIndexer) : FEMALE
+ (s:DecFromIndexer) : MALE
+ val ls = for ntf in generate-entry(name(s),type(s)) map :
+ val n = name(ntf)
+ val dec-gender = default-gender * flip(ntf)
for x in ctable[n] do :
- if (flip(x) * MALE) == lgender : error("Shouldn't be here")
- val rgender = lgender * REVERSE
- val l* = set-gender(exp(l),lgender,flip(l))
- val exps = to-list $ for e in ctable[n] map : set-gender(exp(e),rgender,flip(e))
- switch fn ([x,y]) : lgender == x and rgender == y :
- [FEMALE,MALE] : ConnectFromIndexed(info(s),index*,l*,exps)
- [MALE,FEMALE] : ConnectToIndexed(info(s),index*,exps,l*)
- (s:ConnectToIndexed) : Begin(ls) where :
- val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash)
- val index* = exp(head $ expand-expr(index(s)))
- for e in locs(s) do :
- for (l in expand-expr(e),r in expand-expr(exp(s))) do :
- val n = name(exp(r) as WRef)
- val x = get?(ctable,n,Vector<EF>())
- add(x,l)
- ctable[n] = x
- val ls = for r in expand-expr(exp(s)) map :
- val n = name(exp(r) as WRef)
- val rgender = MALE * flip(r)
- for x in ctable[n] do :
- if (flip(x) * FEMALE) == rgender : error("Shouldn't be here")
- val lgender = rgender * REVERSE
- val r* = set-gender(exp(r),rgender,flip(r))
- val locs = to-list $ for e in ctable[n] map : set-gender(exp(e),lgender,flip(e))
- switch fn ([x,y]) : lgender == x and rgender == y :
- [FEMALE,MALE] : ConnectToIndexed(info(s),index*,locs,r*)
- [MALE,FEMALE] : ConnectFromIndexed(info(s),index*,r*,locs)
+ if (flip(x) * swap(default-gender)) == dec-gender :
+ error("Shouldn't be here")
+ val exps-gender = swap(dec-gender)
+ ;val l* = set-gender(exp(l),lgender,flip(ntf))
+ val exps = to-list $ for e in ctable[n] map :
+ set-gender(exp(e),exps-gender,flip(e))
+ switch fn ([x,y]) : dec-gender == x and exps-gender == y :
+ [FEMALE,MALE] : DecToIndexer(info(s),index*,exps,name(ntf),type(ntf))
+ [MALE,FEMALE] : DecFromIndexer(info(s),index*,exps,name(ntf),type(ntf))
(s:Conditionally) :
Conditionally(info(s),exp(head $ expand-expr(pred(s))),lower-stmt(conseq(s)),lower-stmt(alt(s)))
(s:Begin|EmptyStmt) : map(lower-stmt,s)
@@ -1154,66 +1136,152 @@ defn lower-to-ground (c:Circuit) -> Circuit :
;;=========== CONVERT MULTI CONNECTS to WHEN ================
-; This pass converts ConnectToIndexed and ConnectFromIndexed
+; This pass converts DecFromIndexer and DecToIndexer
; into a series of when statements. TODO what about initial
; values?
-public defstruct ExpandIndexedConnects <: Pass
-public defmethod pass (b:ExpandIndexedConnects) -> (Circuit -> Circuit) : expand-connect-indexed
-public defmethod name (b:ExpandIndexedConnects) -> String : "Expand Indexed Connects"
-public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexed-connects"
-
-defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
- defn equality (e1:Expression,e2:Expression) -> Expression :
- DoPrim(EQUIV-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
- defn get-name (e:Expression) -> Symbol :
- match(e) :
- (e:WRef) : name(e)
- (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)])
- (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))])
- (e) : `T
- match(s) :
- (s:ConnectToIndexed) : Begin $
- if length(locs(s)) == 0 : list(EmptyStmt())
- else :
- val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
- append(
- list(DefNode(info(s),name(ref),index(s)))
- to-list $
- for (i in 0 to false, l in locs(s)) stream : Conditionally(
- info(s),
- equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
- Connect(info(s),l,exp(s)),
- EmptyStmt()
- )
- )
- (s:ConnectFromIndexed) : Begin $
- if length(exps(s)) == 0 : list(EmptyStmt())
- else :
- val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
- append(
- list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s)))
- to-list $
- for (i in 1 to false, e in tail(exps(s))) stream : Conditionally(
- info(s),
- equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
- Connect(info(s),loc(s),e),
- EmptyStmt()
- )
- )
- (s) : map(expand-connect-indexed-stmt{_,sh},s)
-
-defn expand-connect-indexed (m: Module) -> Module :
- match(m) :
- (m:InModule) :
- val sh = get-sym-hash(m,keys(v-keywords))
- InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh))
- (m:ExModule) : m
+;public defstruct ExpandIndexedConnects <: Pass
+;public defmethod pass (b:ExpandIndexedConnects) -> (Circuit -> Circuit) : expand-connect-indexed
+;public defmethod name (b:ExpandIndexedConnects) -> String : "Expand Indexed Connects"
+;public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexed-connects"
+;
+;defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
+; defn equality (e1:Expression,e2:Expression) -> Expression :
+; DoPrim(EQUIV-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
+; defn get-name (e:Expression) -> Symbol :
+; match(e) :
+; (e:WRef) : name(e)
+; (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)])
+; (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))])
+; (e) : `T
+; match(s) :
+; (s:DecFromIndexer) : Begin $
+; if length(locs(s)) == 0 : list(EmptyStmt())
+; else :
+; val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+; append(
+; list(DefNode(info(s),name(ref),index(s)))
+; to-list $
+; for (i in 0 to false, l in locs(s)) stream : Conditionally(
+; info(s),
+; equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
+; Connect(info(s),l,exp(s)),
+; EmptyStmt()
+; )
+; )
+; (s:DecToIndexer) : Begin $
+; if length(exps(s)) == 0 : list(EmptyStmt())
+; else :
+; val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+; append(
+; list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s)))
+; to-list $
+; for (i in 1 to false, e in tail(exps(s))) stream : Conditionally(
+; info(s),
+; equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
+; Connect(info(s),loc(s),e),
+; EmptyStmt()
+; )
+; )
+; (s) : map(expand-connect-indexed-stmt{_,sh},s)
+;
+;defn expand-connect-indexed (m: Module) -> Module :
+; match(m) :
+; (m:InModule) :
+; val sh = get-sym-hash(m,keys(v-keywords))
+; InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh))
+; (m:ExModule) : m
+;
+;defn expand-connect-indexed (c: Circuit) -> Circuit :
+; Circuit(info(c),modules*, main(c)) where :
+; val modules* =
+; for m in modules(c) map :
+; expand-connect-indexed(m)
+
+;;================ INLINE ACCESSORS =========================
+; This pass inlines all accessors to non-memory vector typed
+; components.
-defn expand-connect-indexed (c: Circuit) -> Circuit :
- Circuit(info(c),modules*, main(c)) where :
- val modules* =
- for m in modules(c) map :
- expand-connect-indexed(m)
+public defstruct InlineIndexed <: Pass
+public defmethod pass (b:InlineIndexed) -> (Circuit -> Circuit) : inline-indexed
+public defmethod name (b:InlineIndexed) -> String : "Inline Indexers"
+public defmethod short-name (b:InlineIndexed) -> String : "inline-indexers"
+
+;------------ Helper Functions --------------
+defn get-name (e:Expression) -> Symbol :
+ match(e) :
+ (e:WRef) : name(e)
+ (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)])
+ (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))])
+ (e) : `T
+
+defn equality (e1:Expression,i:Int) -> Expression :
+ DoPrim(EQUIV-OP,list(e1,UIntValue(BigIntLit(i),UnknownWidth())),
+ List(),UIntType(UnknownWidth()))
+
+defn expand-indexed (indexer:WRef,
+ indexed-dec:Stmt,
+ stmts:Vector<Stmt>,
+ sh:HashTable<Symbol,Int>) -> Expression :
+
+ val index = index(indexed-dec as DecFromIndexer|DecToIndexer)
+ val index-name = firrtl-gensym(get-name(index),sh)
+ val index-ref = WRef(index-name,type(index),NodeKind(),MALE)
+
+ val replace-name = firrtl-gensym(get-name(indexer),sh)
+ val replace-ref = WRef(replace-name,type(indexer),kind(indexer),gender(indexer))
+
+ add(stmts, DefWire(info(indexed-dec),name(replace-ref),type(replace-ref)))
+ add(stmts, DefNode(info(indexed-dec),index-name,index))
+ match(indexed-dec) :
+ (s:DecFromIndexer) :
+ if (gender(replace-ref) != FEMALE) : error("Shouldn't be here")
+ for (i in 0 to false, e in exps(s)) do :
+ val eq = equality(index-ref,i)
+ add(stmts,Conditionally(info(s),eq,
+ Connect(info(s),e,replace-ref),EmptyStmt()))
+ (s:DecToIndexer) :
+ if (gender(replace-ref) != MALE) : error("Shouldn't be here")
+ add(stmts,Connect(info(s),replace-ref,head(exps(s))))
+ ;println-all(["exps: " exps(s)])
+ for (i in 1 to false, e in tail(exps(s))) do :
+ val eq = equality(index-ref,i)
+ add(stmts,Conditionally(info(s),eq,Connect(info(s),replace-ref,e),EmptyStmt()))
+ replace-ref
+
+;------------- Inline Accessors -------------
+
+defn inline-indexed-m (m:InModule) -> InModule :
+ val sh = get-sym-hash(m,keys(v-keywords))
+ val indexed-hash = HashTable<Symbol,Stmt>(symbol-hash)
+
+ defn inline-indexed-s (s:Stmt) -> Stmt :
+ val stmts = Vector<Stmt>()
+ defn inline-indexed-e (e:Expression) -> Expression :
+ match(map(inline-indexed-e,e)) :
+ (e:WRef) :
+ if key?(indexed-hash,name(e)) :
+ val indexer = indexed-hash[name(e)]
+ map(inline-indexed-e,indexer)
+ expand-indexed(e,indexer,stmts,sh)
+ else : e
+ (e) : e
+ match(s) :
+ (s:DecFromIndexer|DecToIndexer) :
+ indexed-hash[name(s)] = s
+ add(stmts,EmptyStmt())
+ (s) :
+ val s* = map(inline-indexed-e,s)
+ add(stmts,map(inline-indexed-s,s*))
+ Begin(to-list(stmts))
+
+ InModule(info(m),name(m),ports(m),inline-indexed-s(body(m)))
+
+public defn inline-indexed (c:Circuit) -> Circuit :
+ Circuit{info(c),_,main(c)} $
+ for m in modules(c) map :
+ match(m) :
+ (m:ExModule) : m
+ (m:InModule) : inline-indexed-m(m)
;;================ EXPAND WHENS =============================
; This pass does three things: remove last connect semantics,
@@ -2258,8 +2326,8 @@ defn to-real-ir (c:Circuit) :
(e) : e
defn to-stmt (s:Stmt) :
match(map(to-exp,s)) :
- (e:ConnectToIndexed) : error("Shouldn't be here")
- (e:ConnectFromIndexed) : error("Shouldn't be here")
+ (e:DecFromIndexer) : error("Shouldn't be here")
+ (e:DecToIndexer) : error("Shouldn't be here")
(e) : map(to-stmt,e)
Circuit(info(c),modules*, main(c)) where :
diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir
new file mode 100644
index 00000000..7f5a4eb8
--- /dev/null
+++ b/test/passes/expand-accessors/simple.fir
@@ -0,0 +1,15 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+ module top :
+ output o : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ i := UInt("h1")
+ infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32>
+ o := a
+
+
diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir
new file mode 100644
index 00000000..54f8a507
--- /dev/null
+++ b/test/passes/expand-accessors/simple2.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+ module top :
+ output o1 : UInt
+ output o2 : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ i := UInt("h1")
+ infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32>
+ o1 := a
+ o2 := a
+
+
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
index c41794e3..c41794e3 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/inline-indexers/bundle-vecs.fir
diff --git a/test/passes/expand-connect-indexed/init-vecs.fir b/test/passes/inline-indexers/init-vecs.fir
index 7d64a117..7d64a117 100644
--- a/test/passes/expand-connect-indexed/init-vecs.fir
+++ b/test/passes/inline-indexers/init-vecs.fir
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
new file mode 100644
index 00000000..ca65977b
--- /dev/null
+++ b/test/passes/inline-indexers/simple.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ output o : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ i := UInt("h1")
+ infer accessor a = m[i]
+ o := a
+
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
new file mode 100644
index 00000000..a334b626
--- /dev/null
+++ b/test/passes/inline-indexers/simple2.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ output o1 : UInt
+ output o2 : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ i := UInt("h1")
+ infer accessor a = m[i]
+ o1 := a
+ o2 := a
+
+;CHECK: wire a : UInt<32>
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: wire a_1 : UInt<32>
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_1 := m$1
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
new file mode 100644
index 00000000..fd8d1418
--- /dev/null
+++ b/test/passes/inline-indexers/simple3.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ input in : UInt<32>
+ input i : UInt<1>
+ wire m : UInt<32>[2]
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ infer accessor a = m[i]
+ a := in
+
+;CHECK: wire a : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
new file mode 100644
index 00000000..dce8f26f
--- /dev/null
+++ b/test/passes/inline-indexers/simple4.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ input in : {x : UInt<32>, y : UInt<32>}
+ input i : UInt<1>
+ wire m : {x : UInt<32>, y : UInt<32>}[2]
+ m[0].x := UInt("h1")
+ m[0].y := UInt("h1")
+ m[1].x := UInt("h1")
+ m[1].y := UInt("h1")
+ infer accessor a = m[i]
+ a.x := in.x
+
+;CHECK: wire a$x : UInt<32>
+;CHECK: node i_1 = i
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x
+;CHECK: a$x := in$x
+;CHECK: Finished Inline Indexers
+;CHECK: Done!
+
+
+
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
new file mode 100644
index 00000000..8cd7bec1
--- /dev/null
+++ b/test/passes/inline-indexers/simple5.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ output o : UInt
+ o := UInt(1)
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] := UInt("h1")
+ m[1] := UInt("h1")
+ i := UInt("h1")
+ when i :
+ infer accessor a = m[i]
+ o := a
+
+;CHECK: when i :
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: Finished Inline Indexers
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
new file mode 100644
index 00000000..98b28611
--- /dev/null
+++ b/test/passes/inline-indexers/simple6.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+ module top :
+ input value : UInt<32>
+ input in : {x : UInt<32>, y : UInt<32>}
+ wire m :{x : UInt<32>, y : UInt<32>}[2][2]
+ wire i : UInt
+
+ m[0][0] := in
+ m[1][0] := in
+ m[0][1] := in
+ m[1][1] := in
+ i := UInt("h1")
+
+ write accessor a = m[i]
+ write accessor b = a[i]
+ b.x := value
+
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+
+
+
+;CHECK: Done!
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 11:56:11 +0000