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| author | Howard Mao | 2016-08-25 20:06:43 -0700 |
|---|---|---|
| committer | Howard Mao | 2016-08-25 20:06:48 -0700 |
| commit | a2af16c1fb1f5166eab34188df9944012da3cbc3 (patch) | |
| tree | f92b7d24794c56be31bf5d9ab3859537e3debd4a /utils | |
| parent | e69d44fc944b5d93c852d54911ce7cf61abb6dd1 (diff) | |
emit wires instead of registers for invalid randomization
Before, the verilog emitter would connect registers to the invalid ports
and use random initialization on the generated registers.
It is better to generate wires instead and use random assignment on the
wires.
Diffstat (limited to 'utils')
0 files changed, 0 insertions, 0 deletions