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authorAlan L2023-02-03 15:38:07 +0800
committerGitHub2023-02-03 07:38:07 +0000
commit94d425f0f48e84bbae1be9d44d64615a37d960d8 (patch)
tree4c00cf409512bc37420402cee2107f495f966979 /utils
parent84a7db57c1429df8ff4cb48010c3fa1e98eb9887 (diff)
Fix invalid references generated by VerilogMemDelays (#2588)
Transformation of mem readwriters whose address contain references to readwriters of mems declared before it would contain invalid references to untransformed memory readwriter, as the connection is not transformed. This commit fixes this issue.
Diffstat (limited to 'utils')
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