Merge pull request #3 from jackbackrack/master

new chisel3 tests

22 files changed, 614 insertions, 0 deletions

diff --git a/test/chisel3/BitsOps.fir b/test/chisel3/BitsOps.fir
new file mode 100644
index 00000000..5fa56b60
--- /dev/null
+++ b/test/chisel3/BitsOps.fir
@@ -0,0 +1,17 @@
+circuit BitsOps : 
+  module BitsOps : 
+    input b : UInt(16)
+    input a : UInt(16)
+    output notout : UInt(16)
+    output andout : UInt(16)
+    output orout : UInt(16)
+    output xorout : UInt(16)
+    
+    node T_13 : UInt = bit-not(a)
+    notout := T_13
+    node T_14 : UInt = bit-and(a, b)
+    andout := T_14
+    node T_15 : UInt = bit-or(a, b)
+    orout := T_15
+    node T_16 : UInt = bit-xor(a, b)
+    xorout := T_16
\ No newline at end of file
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
new file mode 100644
index 00000000..72d3061e
--- /dev/null
+++ b/test/chisel3/BundleWire.fir
@@ -0,0 +1,14 @@
+circuit BundleWire : 
+  module BundleWire : 
+    output in : {input y : UInt(32), input x : UInt(32)}
+    output outs : {output y : UInt(32), output x : UInt(32)}[4]
+    
+    wire coords : {output y : UInt(32), output x : UInt(32)}[4]
+    coords.0 := in
+    outs.0 := coords.0
+    coords.1 := in
+    outs.1 := coords.1
+    coords.2 := in
+    outs.2 := coords.2
+    coords.3 := in
+    outs.3 := coords.3
\ No newline at end of file
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
new file mode 100644
index 00000000..2cf52370
--- /dev/null
+++ b/test/chisel3/ComplexAssign.fir
@@ -0,0 +1,15 @@
+circuit ComplexAssign : 
+  module ComplexAssign : 
+    input in : {output re : UInt(10), output im : UInt(10)}
+    output out : {output re : UInt(10), output im : UInt(10)}
+    input e : UInt(1)
+    when e : 
+      wire T_19 : {output re : UInt(10), output im : UInt(10)}
+      T_19 := in
+      out.re := T_19.re
+      out.im := T_19.im
+     else : 
+      node T_20 : UInt(1) = UInt(0, 1)
+      out.re := T_20
+      node T_21 : UInt(1) = UInt(0, 1)
+      out.im := T_21
\ No newline at end of file
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
new file mode 100644
index 00000000..8bab249c
--- /dev/null
+++ b/test/chisel3/Counter.fir
@@ -0,0 +1,17 @@
+circuit Counter : 
+  module Counter : 
+    input inc : UInt(1)
+    output tot : UInt(8)
+    input amt : UInt(4)
+    
+    node T_13 : UInt(8) = UInt(255, 8)
+    node T_14 : UInt(8) = UInt(0, 8)
+    reg T_15 : UInt(8)
+    T_15.init := T_14
+    when inc : 
+      node T_16 : UInt = add-mod(T_15, amt)
+      node T_17 : UInt(1) = greater(T_16, T_13)
+      node T_18 : UInt(1) = UInt(0, 1)
+      node T_19 : UInt(1) = multiplex(T_17, T_18, T_16)
+      T_15 := T_19
+    tot := T_15
\ No newline at end of file
diff --git a/test/chisel3/DirChange.fir b/test/chisel3/DirChange.fir
new file mode 100644
index 00000000..c948dc85
--- /dev/null
+++ b/test/chisel3/DirChange.fir
@@ -0,0 +1,7 @@
+circuit DirChange : 
+  module DirChange : 
+    input test1 : UInt(5)
+    output test2 : UInt(5)
+    input test3 : UInt(2)[10]
+    output test4 : {output test41 : UInt(5), output test42 : UInt(5)}
+    skip
\ No newline at end of file
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
new file mode 100644
index 00000000..aa7d36ae
--- /dev/null
+++ b/test/chisel3/EnableShiftRegister.fir
@@ -0,0 +1,24 @@
+circuit EnableShiftRegister : 
+  module EnableShiftRegister : 
+    input in : UInt(4)
+    output out : UInt(4)
+    input shift : UInt(1)
+    
+    node T_14 : UInt(4) = UInt(0, 4)
+    reg r0 : UInt(4)
+    r0.init := T_14
+    node T_15 : UInt(4) = UInt(0, 4)
+    reg r1 : UInt(4)
+    r1.init := T_15
+    node T_16 : UInt(4) = UInt(0, 4)
+    reg r2 : UInt(4)
+    r2.init := T_16
+    node T_17 : UInt(4) = UInt(0, 4)
+    reg r3 : UInt(4)
+    r3.init := T_17
+    when shift : 
+      r0 := in
+      r1 := r0
+      r2 := r1
+      r3 := r2
+    out := r3
\ No newline at end of file
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
new file mode 100644
index 00000000..5b103a6b
--- /dev/null
+++ b/test/chisel3/GCD.fir
@@ -0,0 +1,24 @@
+circuit GCD : 
+  module GCD : 
+    input b : UInt(16)
+    input a : UInt(16)
+    input e : UInt(1)
+    output z : UInt(16)
+    output v : UInt(1)
+    
+    reg x : UInt(16)
+    reg y : UInt(16)
+    node T_17 : UInt(1) = greater(x, y)
+    when T_17 : 
+      node T_18 : UInt = sub-mod(x, y)
+      x := T_18
+     else : 
+      node T_19 : UInt = sub-mod(y, x)
+      y := T_19
+    when e : 
+      x := a
+      y := b
+    z := x
+    node T_20 : UInt(1) = UInt(0, 1)
+    node T_21 : UInt(1) = equal(y, T_20)
+    v := T_21
\ No newline at end of file
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
new file mode 100644
index 00000000..7e661548
--- /dev/null
+++ b/test/chisel3/LFSR16.fir
@@ -0,0 +1,20 @@
+circuit LFSR16 : 
+  module LFSR16 : 
+    output out : UInt(16)
+    input inc : UInt(1)
+    
+    node T_16 : UInt(16) = UInt(1, 16)
+    reg res : UInt(16)
+    res.init := T_16
+    when inc : 
+      node T_17 : UInt(1) = bit(res, 0)
+      node T_18 : UInt(1) = bit(res, 2)
+      node T_19 : UInt(1) = bit-xor(T_17, T_18)
+      node T_20 : UInt(1) = bit(res, 3)
+      node T_21 : UInt(1) = bit-xor(T_19, T_20)
+      node T_22 : UInt(1) = bit(res, 5)
+      node T_23 : UInt(1) = bit-xor(T_21, T_22)
+      node T_24 : UInt = bits(res, 15, 1)
+      node T_25 : UInt(1) = concat(T_23, T_24)
+      res := T_25
+    out := res
\ No newline at end of file
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
new file mode 100644
index 00000000..f7a0fb84
--- /dev/null
+++ b/test/chisel3/MemorySearch.fir
@@ -0,0 +1,43 @@
+circuit MemorySearch : 
+  module MemorySearch : 
+    input target : UInt(4)
+    output address : UInt(3)
+    input en : UInt(1)
+    output done : UInt(1)
+    
+    node T_36 : UInt(3) = UInt(0, 3)
+    reg index : UInt(3)
+    index.init := T_36
+    node T_37 : UInt(1) = UInt(0, 1)
+    node T_38 : UInt(3) = UInt(4, 3)
+    node T_39 : UInt(4) = UInt(15, 4)
+    node T_40 : UInt(4) = UInt(14, 4)
+    node T_41 : UInt(2) = UInt(2, 2)
+    node T_42 : UInt(3) = UInt(5, 3)
+    node T_43 : UInt(4) = UInt(13, 4)
+    wire elts : UInt(1)[7]
+    elts.0 := T_37
+    elts.1 := T_38
+    elts.2 := T_39
+    elts.3 := T_40
+    elts.4 := T_41
+    elts.5 := T_42
+    elts.6 := T_43
+    accessor elt = elts[index]
+    node T_44 : UInt(1) = bit-not(en)
+    node T_45 : UInt(1) = equal(elt, target)
+    node T_46 : UInt(3) = UInt(7, 3)
+    node T_47 : UInt(1) = equal(index, T_46)
+    node T_48 : UInt(1) = bit-or(T_45, T_47)
+    node done : UInt(1) = bit-and(T_44, T_48)
+    when en : 
+      node T_49 : UInt(1) = UInt(0, 1)
+      index := T_49
+     else : 
+      node T_50 : UInt(1) = bit-not(done)
+      when T_50 : 
+        node T_51 : UInt(1) = UInt(1, 1)
+        node T_52 : UInt(3) = add(index, T_51)
+        index := T_52
+    done := done
+    address := index
\ No newline at end of file
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
new file mode 100644
index 00000000..1372d1f6
--- /dev/null
+++ b/test/chisel3/ModuleVec.fir
@@ -0,0 +1,25 @@
+circuit ModuleVec : 
+  module PlusOne : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_34 : UInt(1) = UInt(1, 1)
+    node T_35 : UInt(32) = add(in, T_34)
+    out := T_35
+  module PlusOne_26 : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_36 : UInt(1) = UInt(1, 1)
+    node T_37 : UInt(32) = add(in, T_36)
+    out := T_37
+  module ModuleVec : 
+    input ins : UInt(32)[2]
+    output outs : UInt(32)[2]
+    
+    instance T_38 of PlusOne
+    instance T_39 of PlusOne_26
+    pluses.0.in := ins.0
+    outs.0 := pluses.0.out
+    pluses.1.in := ins.1
+    outs.1 := pluses.1.out
\ No newline at end of file
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
new file mode 100644
index 00000000..f8ba0b78
--- /dev/null
+++ b/test/chisel3/Mul.fir
@@ -0,0 +1,44 @@
+circuit Mul : 
+  module Mul : 
+    input y : UInt(2)
+    input x : UInt(2)
+    output z : UInt(4)
+    
+    node T_44 : UInt(4) = UInt(0, 4)
+    node T_45 : UInt(4) = UInt(0, 4)
+    node T_46 : UInt(4) = UInt(0, 4)
+    node T_47 : UInt(4) = UInt(0, 4)
+    node T_48 : UInt(4) = UInt(0, 4)
+    node T_49 : UInt(4) = UInt(1, 4)
+    node T_50 : UInt(4) = UInt(2, 4)
+    node T_51 : UInt(4) = UInt(3, 4)
+    node T_52 : UInt(4) = UInt(0, 4)
+    node T_53 : UInt(4) = UInt(2, 4)
+    node T_54 : UInt(4) = UInt(4, 4)
+    node T_55 : UInt(4) = UInt(6, 4)
+    node T_56 : UInt(4) = UInt(0, 4)
+    node T_57 : UInt(4) = UInt(3, 4)
+    node T_58 : UInt(4) = UInt(6, 4)
+    node T_59 : UInt(4) = UInt(9, 4)
+    wire tbl : UInt(4)[16]
+    tbl.0 := T_44
+    tbl.1 := T_45
+    tbl.2 := T_46
+    tbl.3 := T_47
+    tbl.4 := T_48
+    tbl.5 := T_49
+    tbl.6 := T_50
+    tbl.7 := T_51
+    tbl.8 := T_52
+    tbl.9 := T_53
+    tbl.10 := T_54
+    tbl.11 := T_55
+    tbl.12 := T_56
+    tbl.13 := T_57
+    tbl.14 := T_58
+    tbl.15 := T_59
+    node T_60 : UInt(2) = UInt(2, 2)
+    node T_61 : UInt(2) = shift-left(x, T_60)
+    node T_62 : UInt(2) = bit-or(T_61, y)
+    accessor T_63 = tbl[T_62]
+    z := T_63
\ No newline at end of file
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
new file mode 100644
index 00000000..e3a67a6e
--- /dev/null
+++ b/test/chisel3/Outer.fir
@@ -0,0 +1,17 @@
+circuit Outer : 
+  module Inner : 
+    input in : UInt(8)
+    output out : UInt(8)
+    
+    node T_15 : UInt(1) = UInt(1, 1)
+    node T_16 : UInt(8) = add(in, T_15)
+    out := T_16
+  module Outer : 
+    input in : UInt(8)
+    output out : UInt(8)
+    
+    instance T_17 of Inner
+    T_17.in := in
+    node T_18 : UInt(2) = UInt(2, 2)
+    node T_19 : UInt(8) = times(T_17.out, T_18)
+    out := T_19
\ No newline at end of file
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
new file mode 100644
index 00000000..772c3d54
--- /dev/null
+++ b/test/chisel3/RegisterVecShift.fir
@@ -0,0 +1,34 @@
+circuit RegisterVecShift : 
+  module RegisterVecShift : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when reset : 
+      node T_39 : UInt(4) = UInt(0, 4)
+      node T_40 : UInt(4) = UInt(0, 4)
+      node T_41 : UInt(4) = UInt(0, 4)
+      node T_42 : UInt(4) = UInt(0, 4)
+      wire T_43 : UInt(4)[4]
+      T_43.0 := T_39
+      T_43.1 := T_40
+      T_43.2 := T_41
+      T_43.3 := T_42
+      delays := T_43
+    node T_44 : UInt(3) = UInt(5, 3)
+    node T_45 : UInt(3) = bit-and(T_44, load)
+    node T_46 : UInt(3) = UInt(4, 3)
+    node T_47 : UInt(1) = equal(T_45, T_46)
+    when T_47 : 
+      delays.0 := ins.0
+      delays.1 := ins.1
+      delays.2 := ins.2
+      delays.3 := ins.3
+     else : when shift : 
+        delays.0 := ins.0
+        delays.1 := delays.0
+        delays.2 := delays.1
+        delays.3 := delays.2
+    out := delays.3
\ No newline at end of file
diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir
new file mode 100644
index 00000000..1a4d21e5
--- /dev/null
+++ b/test/chisel3/Risc.fir
@@ -0,0 +1,66 @@
+circuit Risc : 
+  module Risc : 
+    output out : UInt(32)
+    output valid : UInt(1)
+    input boot : UInt(1)
+    input isWr : UInt(1)
+    input wrAddr : UInt(8)
+    input wrData : UInt(32)
+    
+    mem file : UInt(32)[256]
+    mem code : UInt(32)[256]
+    node T_51 : UInt(8) = UInt(0, 8)
+    reg pc : UInt(8)
+    pc.init := T_51
+    node add_op : UInt(1) = UInt(0, 1)
+    node imm_op : UInt(1) = UInt(1, 1)
+    accessor inst = code[pc]
+    node op : UInt = bits(inst, 31, 24)
+    node rci : UInt = bits(inst, 23, 16)
+    node rai : UInt = bits(inst, 15, 8)
+    node rbi : UInt = bits(inst, 7, 0)
+    node T_52 : UInt(1) = UInt(0, 1)
+    node T_53 : UInt(1) = equal(rai, T_52)
+    node T_54 : UInt(1) = UInt(0, 1)
+    accessor T_55 = file[rai]
+    node ra : UInt = multiplex(T_53, T_54, T_55)
+    node T_56 : UInt(1) = UInt(0, 1)
+    node T_57 : UInt(1) = equal(rbi, T_56)
+    node T_58 : UInt(1) = UInt(0, 1)
+    accessor T_59 = file[rbi]
+    node rb : UInt = multiplex(T_57, T_58, T_59)
+    wire rc : UInt(32)
+    node T_60 : UInt(1) = UInt(0, 1)
+    valid := T_60
+    node T_61 : UInt(1) = UInt(0, 1)
+    out := T_61
+    node T_62 : UInt(1) = UInt(0, 1)
+    rc := T_62
+    when isWr : 
+      accessor T_63 = code[wrAddr]
+      T_63 := wrData
+    else : when boot : 
+        node T_64 : UInt(1) = UInt(0, 1)
+        pc := T_64
+      else : 
+        node T_65 : UInt(1) = equal(add_op, op)
+        when T_65 : 
+          node T_66 : UInt = add-mod(ra, rb)
+          rc := T_66
+        node T_67 : UInt(1) = equal(imm_op, op)
+        when T_67 : 
+          node T_68 : UInt = shift-left(rai, 8)
+          node T_69 : UInt = bit-or(T_68, rbi)
+          rc := T_69
+        out := rc
+        node T_70 : UInt(8) = UInt(255, 8)
+        node T_71 : UInt(1) = equal(rci, T_70)
+        when T_71 : 
+          node T_72 : UInt(1) = UInt(1, 1)
+          valid := T_72
+        else : 
+          accessor T_73 = file[rci]
+          T_73 := rc
+        node T_74 : UInt(1) = UInt(1, 1)
+        node T_75 : UInt = add-mod(pc, T_74)
+        pc := T_75
\ No newline at end of file
diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir
new file mode 100644
index 00000000..bb4960a4
--- /dev/null
+++ b/test/chisel3/Rom.fir
@@ -0,0 +1,24 @@
+circuit Rom : 
+  module Rom : 
+    output out : UInt(8)
+    input addr : UInt(8)
+    
+    node T_24 : UInt(8) = UInt(0, 8)
+    node T_25 : UInt(8) = UInt(1, 8)
+    node T_26 : UInt(8) = UInt(2, 8)
+    node T_27 : UInt(8) = UInt(3, 8)
+    node T_28 : UInt(8) = UInt(4, 8)
+    node T_29 : UInt(8) = UInt(5, 8)
+    node T_30 : UInt(8) = UInt(6, 8)
+    node T_31 : UInt(8) = UInt(7, 8)
+    wire r : UInt(8)[8]
+    r.0 := T_24
+    r.1 := T_25
+    r.2 := T_26
+    r.3 := T_27
+    r.4 := T_28
+    r.5 := T_29
+    r.6 := T_30
+    r.7 := T_31
+    accessor T_32 = r[addr]
+    out := T_32
\ No newline at end of file
diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir
new file mode 100644
index 00000000..b026e1f3
--- /dev/null
+++ b/test/chisel3/SIntOps.fir
@@ -0,0 +1,49 @@
+circuit SIntOps : 
+  module SIntOps : 
+    input b : UInt(16)
+    input a : UInt(16)
+    output addout : UInt(16)
+    output subout : UInt(16)
+    output timesout : UInt(16)
+    output divout : UInt(16)
+    output modout : UInt(16)
+    output lshiftout : UInt(16)
+    output rshiftout : UInt(16)
+    output lessout : UInt(1)
+    output greatout : UInt(1)
+    output eqout : UInt(1)
+    output noteqout : UInt(1)
+    output lesseqout : UInt(1)
+    output greateqout : UInt(1)
+    output negout : UInt(16)
+    
+    node T_35 : UInt = add-mod(a, b)
+    addout := T_35
+    node T_36 : UInt = sub-mod(a, b)
+    subout := T_36
+    node T_37 : UInt = times(a, b)
+    node T_38 : UInt = bits(T_37, 15, 0)
+    timesout := T_38
+    node T_39 : UInt = divide(a, b)
+    divout := T_39
+    node T_40 : UInt = divide(a, b)
+    modout := T_40
+    node T_41 : UInt = shift-left(a, 12)
+    node T_42 : UInt = bits(T_41, 15, 0)
+    lshiftout := T_42
+    node T_43 : UInt = shift-right(a, 8)
+    rshiftout := T_43
+    node T_44 : UInt(1) = less(a, b)
+    lessout := T_44
+    node T_45 : UInt(1) = greater(a, b)
+    greatout := T_45
+    node T_46 : UInt(1) = equal(a, b)
+    eqout := T_46
+    node T_47 : UInt(1) = not-equal(a, b)
+    noteqout := T_47
+    node T_48 : UInt(1) = less-eq(a, b)
+    lesseqout := T_48
+    node T_49 : UInt(1) = greater-eq(a, b)
+    greateqout := T_49
+    node T_50 : UInt = neg(a)
+    negout := T_50
\ No newline at end of file
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
new file mode 100644
index 00000000..15596d0d
--- /dev/null
+++ b/test/chisel3/Stack.fir
@@ -0,0 +1,41 @@
+circuit Stack : 
+  module Stack : 
+    input push : UInt(1)
+    input pop : UInt(1)
+    input en : UInt(1)
+    output dataOut : UInt(32)
+    input dataIn : UInt(32)
+    
+    mem stack_mem : UInt(32)[16]
+    node T_30 : UInt(5) = UInt(0, 5)
+    reg sp : UInt(5)
+    sp.init := T_30
+    node T_31 : UInt(32) = UInt(0, 32)
+    reg out : UInt(32)
+    out.init := T_31
+    when en : 
+      node T_32 : UInt(5) = UInt(16, 5)
+      node T_33 : UInt(1) = less(sp, T_32)
+      node T_34 : UInt(1) = bit-and(push, T_33)
+      when T_34 : 
+        accessor T_35 = stack_mem[sp]
+        T_35 := dataIn
+        node T_36 : UInt(1) = UInt(1, 1)
+        node T_37 : UInt = add-mod(sp, T_36)
+        sp := T_37
+       else : 
+        node T_38 : UInt(1) = UInt(0, 1)
+        node T_39 : UInt(1) = greater(sp, T_38)
+        node T_40 : UInt(1) = bit-and(pop, T_39)
+        when T_40 : 
+          node T_41 : UInt(1) = UInt(1, 1)
+          node T_42 : UInt = sub-mod(sp, T_41)
+          sp := T_42
+      node T_43 : UInt(1) = UInt(0, 1)
+      node T_44 : UInt(1) = greater(sp, T_43)
+      when T_44 : 
+        node T_45 : UInt(1) = UInt(1, 1)
+        node T_46 : UInt = sub-mod(sp, T_45)
+        accessor T_47 = stack_mem[T_46]
+        out := T_47
+    dataOut := out
\ No newline at end of file
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
new file mode 100644
index 00000000..273047b0
--- /dev/null
+++ b/test/chisel3/Tbl.fir
@@ -0,0 +1,16 @@
+circuit Tbl : 
+  module Tbl : 
+    output o : UInt(16)
+    input i : UInt(16)
+    input d : UInt(16)
+    input we : UInt(1)
+    
+    mem m : UInt(10)[256]
+    node T_13 : UInt(1) = UInt(0, 1)
+    o := T_13
+    when we : 
+      accessor T_14 = m[i]
+      T_14 := d
+     else : 
+      accessor T_15 = m[i]
+      o := T_15
\ No newline at end of file
diff --git a/test/chisel3/UIntOps.fir b/test/chisel3/UIntOps.fir
new file mode 100644
index 00000000..8d0e105e
--- /dev/null
+++ b/test/chisel3/UIntOps.fir
@@ -0,0 +1,44 @@
+circuit UIntOps : 
+  module UIntOps : 
+    input b : UInt(16)
+    input a : UInt(16)
+    output addout : UInt(16)
+    output subout : UInt(16)
+    output timesout : UInt(16)
+    output divout : UInt(16)
+    output modout : UInt(16)
+    output lshiftout : UInt(16)
+    output rshiftout : UInt(16)
+    output lessout : UInt(1)
+    output greatout : UInt(1)
+    output eqout : UInt(1)
+    output noteqout : UInt(1)
+    output lesseqout : UInt(1)
+    output greateqout : UInt(1)
+    
+    node T_32 : UInt(16) = add(a, b)
+    addout := T_32
+    node T_33 : UInt(16) = sub(a, b)
+    subout := T_33
+    node T_34 : UInt(16) = times(a, b)
+    timesout := T_34
+    node T_35 : UInt(16) = divide(a, b)
+    divout := T_35
+    node T_36 : UInt(16) = divide(a, b)
+    modout := T_36
+    node T_37 : UInt(16) = shift-left(a, 12)
+    lshiftout := T_37
+    node T_38 : UInt(16) = shift-right(a, 8)
+    rshiftout := T_38
+    node T_39 : UInt(1) = less(a, b)
+    lessout := T_39
+    node T_40 : UInt(1) = greater(a, b)
+    greatout := T_40
+    node T_41 : UInt(1) = equal(a, b)
+    eqout := T_41
+    node T_42 : UInt(1) = not-equal(a, b)
+    noteqout := T_42
+    node T_43 : UInt(1) = less-eq(a, b)
+    lesseqout := T_43
+    node T_44 : UInt(1) = greater-eq(a, b)
+    greateqout := T_44
\ No newline at end of file
diff --git a/test/chisel3/VecApp.fir b/test/chisel3/VecApp.fir
new file mode 100644
index 00000000..6b2bc21d
--- /dev/null
+++ b/test/chisel3/VecApp.fir
@@ -0,0 +1,8 @@
+circuit VecApp : 
+  module VecApp : 
+    input a : UInt(4)
+    input i : UInt(8)[4]
+    output d : UInt(8)
+    
+    accessor T_13 = i[a]
+    d := T_13
\ No newline at end of file
diff --git a/test/chisel3/VecShiftRegister.fir b/test/chisel3/VecShiftRegister.fir
new file mode 100644
index 00000000..86f20796
--- /dev/null
+++ b/test/chisel3/VecShiftRegister.fir
@@ -0,0 +1,19 @@
+circuit VecShiftRegister : 
+  module VecShiftRegister : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when load : 
+      delays.0 := ins.0
+      delays.1 := ins.1
+      delays.2 := ins.2
+      delays.3 := ins.3
+     else : when shift : 
+        delays.0 := ins.0
+        delays.1 := delays.0
+        delays.2 := delays.1
+        delays.3 := delays.2
+    out := delays.3
\ No newline at end of file
diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir
new file mode 100644
index 00000000..4ae94524
--- /dev/null
+++ b/test/chisel3/VendingMachine.fir
@@ -0,0 +1,46 @@
+circuit VendingMachine : 
+  module VendingMachine : 
+    output valid : UInt(1)
+    input nickel : UInt(1)
+    input dime : UInt(1)
+    
+    node T_34 : UInt(3) = UInt(5, 3)
+    wire c : UInt
+    c := T_34
+    node T_35 : UInt(3) = UInt(0, 3)
+    wire sIdle : UInt
+    sIdle := T_35
+    node T_36 : UInt(3) = UInt(1, 3)
+    wire s5 : UInt
+    s5 := T_36
+    node T_37 : UInt(3) = UInt(2, 3)
+    wire s10 : UInt
+    s10 := T_37
+    node T_38 : UInt(3) = UInt(3, 3)
+    wire s15 : UInt
+    s15 := T_38
+    node T_39 : UInt(3) = UInt(4, 3)
+    wire sOk : UInt
+    sOk := T_39
+    reg state : UInt
+    state.init := sIdle
+    node T_40 : UInt(1) = equal(state, sIdle)
+    when T_40 : 
+      when nickel : state := s5
+      when dime : state := s10
+    node T_41 : UInt(1) = equal(state, s5)
+    when T_41 : 
+      when nickel : state := s10
+      when dime : state := s15
+    node T_42 : UInt(1) = equal(state, s10)
+    when T_42 : 
+      when nickel : state := s15
+      when dime : state := sOk
+    node T_43 : UInt(1) = equal(state, s15)
+    when T_43 : 
+      when nickel : state := sOk
+      when dime : state := sOk
+    node T_44 : UInt(1) = equal(state, sOk)
+    when T_44 : state := sIdle
+    node T_45 : UInt(1) = equal(state, sOk)
+    valid := T_45
\ No newline at end of file