Still partial commit, many tests pass. Many tests fail.

11 files changed, 82 insertions, 33 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index eb396bcf..0daec379 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -6,15 +6,17 @@ circuit top :
       cmem m : UInt<32>[2][2][2]
       wire i : UInt<4>
       i := UInt(1)
-      accessor a = m[i] ;CHECK: accessor a = m[i]
-      accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
-      accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
+      infer accessor a = m[i] ;CHECK: read accessor a = m[i]
+      infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
+      infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: accessor x = m[i]
-      accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
-      accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
+      infer accessor x = m[i] ;CHECK: write accessor x = m[i]
+      infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
+      y[0] := UInt(1)
+      y[1] := UInt(1)
+      infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
       z := j
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index 81c44d1b..5cdad6c7 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -4,25 +4,43 @@
 circuit top :
    module top :
       wire m : UInt<32>[2][2][2]
+      m[0][0][0] := UInt(1)
+      m[1][0][0] := UInt(1)
+      m[0][1][0] := UInt(1)
+      m[1][1][0] := UInt(1)
+      m[0][0][1] := UInt(1)
+      m[1][0][1] := UInt(1)
+      m[0][1][1] := UInt(1)
+      m[1][1][1] := UInt(1)
       wire i : UInt
       i := UInt(1)
-      accessor a = m[i] ;CHECK: a := (m[0] m[1])[i]
-      accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
-      accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
+      infer accessor a = m[i] ;CHECK: a := (m[0] m[1])[i]
+      infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
+      infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x
-      accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
-      accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
+      infer accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x
+      x[0][0] := UInt(1)
+      x[1][0] := UInt(1)
+      x[0][1] := UInt(1)
+      x[1][1] := UInt(1)
+      infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
+      infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
+      y[0] := UInt(1)
+      y[1] := UInt(1)
       z := j
 
       wire p : {n : UInt<32>[2]}
-      accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q
+      p.n[0] := UInt(1)
+      p.n[1] := UInt(1)
+      infer accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q
       q := j
 
       wire r : {m : UInt<32>}[2]
-      accessor s = r[i] ;CHECK: s := (r[0] r[1])[i]
+      r[0].m := UInt(1)
+      r[1].m := UInt(1)
+      infer accessor s = r[i] ;CHECK: s := (r[0] r[1])[i]
       j := s.m
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 9d375087..ea453ab1 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -12,7 +12,7 @@ circuit top :
       ; CHECK: wire a$1$x : UInt<32>
       ; CHECK: wire a$1$y : UInt<32>
 
-      accessor b = a[i]
+      infer accessor b = a[i]
       ; CHECK: wire b$x : UInt<32>
       ; CHECK: wire b$y : UInt<32>
       ; CHECK: b$x := a$0$x
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 4f8c31e2..261ebf02 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -15,8 +15,8 @@ circuit top :
       r.y := b
       on-reset r := w
 
-; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1))
-; CHECK: r$y := Register(b, UInt(1))
+; CHECK: when UInt(1) : r$x := mux(reset, w$x, a)
+; CHECK: when UInt(1) : r$y := b
 ; CHECK: a := UInt(1)
 ; CHECK: b := UInt(2)
 ; CHECK: w$x := b
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index f7ac8337..4d23a549 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -11,6 +11,14 @@ circuit top :
       wire y : UInt
       wire z : UInt
       wire w : UInt
+      p := UInt(1)
+      q := UInt(1)
+      a := UInt(1)
+      b := UInt(1)
+      x := UInt(1)
+      y := UInt(1)
+      z := UInt(1)
+      w := UInt(1)
 
       on-reset r := w
       when p :
@@ -20,5 +28,5 @@ circuit top :
         on-reset r := y
         r := b
       r := z
-; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
+; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z)
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 114e5b5b..4e6ea1e5 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -7,21 +7,22 @@ circuit top :
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
+      j := UInt(1)
       reg r : UInt<1>
 
       p := j
       when p :
         on-reset r := i
-        accessor a = m[i] 
+        infer accessor a = m[i] 
         i := a
-        accessor b = m[i]
+        infer accessor b = m[i]
         b := i
       else :
-        accessor c = m[i]
+        infer accessor c = m[i]
         i := c
-        accessor d = m[i] 
+        infer accessor d = m[i] 
         d := i
-      accessor e = m[i]
+      infer accessor e = m[i]
       when p :
         p := i
         when e :
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index c9afd86c..03b1f965 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -4,6 +4,16 @@
 circuit top :
    module top :
       reg r : UInt<1>[10]
+      r[0] := UInt(1)
+      r[1] := UInt(1)
+      r[2] := UInt(1)
+      r[3] := UInt(1)
+      r[4] := UInt(1)
+      r[5] := UInt(1)
+      r[6] := UInt(1)
+      r[7] := UInt(1)
+      r[8] := UInt(1)
+      r[9] := UInt(1)
       on-reset r[3] := UInt(0)
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index ad2089c2..ad191a01 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -2,6 +2,7 @@
 circuit top :
    module top :
       wire p : UInt
+      p := UInt(1)
       when p :
          reg r : UInt
          on-reset r := UInt(10)
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index 7f2632f4..d119932f 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -2,6 +2,7 @@
 circuit top :
    module top :
       wire p : UInt
+      p := UInt(1)
       when p :
          reg r : UInt
          on-reset r := UInt(10)
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index fb537303..b6c98263 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -5,31 +5,34 @@ circuit top :
    module top :
       cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
       wire i : UInt<1>
+      i := UInt(1)
       wire p : UInt<1>
+      p := UInt(1)
       wire q : { x : UInt<1>, y : UInt<1> }
       when p :
         wire p2 : UInt<1>
-        reg r5 : UInt<1>
+        p2 := UInt(1)
         when p2 :
-          accessor a = m[i] 
+          infer accessor a = m[i] 
           q := a
-          accessor b = m[i]
+          infer accessor b = m[i]
           b := q
         else :
-          accessor c = m[i] 
+          infer accessor c = m[i] 
           q := c
-          accessor d = m[i]
+          infer accessor d = m[i]
           d := q
       else :
         wire p3 : UInt<1>
+        p3 := UInt(1)
         when p3 :
-          accessor w = m[i] 
+          infer accessor w = m[i] 
           q := w
-          accessor x = m[i]
+          infer accessor x = m[i]
           x := q
         else :
-          accessor y = m[i] 
+          infer accessor y = m[i] 
           q := y
-          accessor z = m[i]
+          infer accessor z = m[i]
           z := q
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 5018aeef..892103d2 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -8,5 +8,10 @@ circuit top :
       node y = z.y            ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
       wire a : UInt<3>[10]    ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
       node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
-      accessor c = a[UInt(3)] ;CHECK: accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)]
+      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)]
 ; CHECK: Finished Infer Types
+; CHECK: Resolve Genders 
+; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)]   
+; CHECK: Finished Resolve Genders 
+
+