merge

39 files changed, 386 insertions, 338 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 96bf8d54..984b6acd 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -3,17 +3,17 @@
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      mem m : UInt(32)[10][10][10]
+      mem m : UInt<32>[10][10][10]
       wire i : UInt
       accessor a = m[i] ;CHECK: accessor a = m[i]
-      accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
-      accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
+      accessor b = a[i] ;CHECK: b := (a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9])[i]
+      accessor c = b[i] ;CHECK: c := (b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9])[i]
       wire j : UInt
       j := c
 
       accessor x = m[i] ;CHECK: accessor x = m[i]
-      accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
-      accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
+      accessor y = x[i] ;CHECK: (x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9])[i] := y
+      accessor z = y[i] ;CHECK: (y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9])[i] := z
       z := j
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index 2c6bbd5f..6d0b5f93 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -3,25 +3,25 @@
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      wire m : UInt(32)[10][10][10]
+      wire m : UInt<32>[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: a := (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i]
-      accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
-      accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
+      accessor a = m[i] ;CHECK: a := (m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] m[9])[i]
+      accessor b = a[i] ;CHECK: b := (a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9])[i]
+      accessor c = b[i] ;CHECK: c := (b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9])[i]
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i] := x
-      accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
-      accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
+      accessor x = m[i] ;CHECK: (m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] m[9])[i] := x
+      accessor y = x[i] ;CHECK: (x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9])[i] := y
+      accessor z = y[i] ;CHECK: (y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9])[i] := z
       z := j
 
-      wire p : {n : UInt(32)[10]}
-      accessor q = p.n[i] ;CHECK: (p.n.0 p.n.1 p.n.2 p.n.3 p.n.4 p.n.5 p.n.6 p.n.7 p.n.8 p.n.9)[i] := q
+      wire p : {n : UInt<32>[10]}
+      accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1] p.n[2] p.n[3] p.n[4] p.n[5] p.n[6] p.n[7] p.n[8] p.n[9])[i] := q
       q := j
 
-      wire r : {m : UInt(32)}[10]
-      accessor s = r[i] ;CHECK: s := (r.0 r.1 r.2 r.3 r.4 r.5 r.6 r.7 r.8 r.9)[i]
+      wire r : {m : UInt<32>}[10]
+      accessor s = r[i] ;CHECK: s := (r[0] r[1] r[2] r[3] r[4] r[5] r[6] r[7] r[8] r[9])[i]
       j := s.m
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 4e6f3456..35b45b6c 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -6,15 +6,15 @@ circuit top :
       wire i : UInt
       wire j : UInt
 
-      wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a$0$x : UInt(32)
-      ; CHECK: wire a$0$y : UInt(32)
-      ; CHECK: wire a$1$x : UInt(32)
-      ; CHECK: wire a$1$y : UInt(32)
+      wire a : { x : UInt<32>, flip y : UInt<32> }[2]
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b$x : UInt(32)
-      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
       ; CHECK: b$x := a$0$x
       ; CHECK: when eq-uu(i, UInt(1)) :
       ; CHECK:    b$x := a$1$x
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
new file mode 100644
index 00000000..48336c93
--- /dev/null
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p cd | tee %s.out | FileCheck %s
+; CHECK: Expand Whens
+circuit top :
+   module A :
+      reg r : { x : UInt, flip y : UInt}
+      wire a : UInt
+      wire b : UInt
+      wire w : { x : UInt, flip y : UInt}
+      a := UInt(1)
+      b := UInt(2)
+
+      w.x := b
+      w.y := a
+      r.x := a
+      r.y := b
+      on-reset r := w
+
+; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1))
+; CHECK: r$y := Register(b, UInt(1))
+; CHECK: a := UInt(1)
+; CHECK: b := UInt(2)
+; CHECK: w$x := b
+; CHECK: w$y := mux-uu(reset, r$y, a)   
+      
+; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
new file mode 100644
index 00000000..8185dade
--- /dev/null
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -0,0 +1,24 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s
+; CHECK: Expand Whens
+circuit top :
+   module A :
+      wire p : UInt
+      wire q : UInt
+      reg r : UInt
+      wire a : UInt
+      wire b : UInt
+      wire x : UInt
+      wire y : UInt
+      wire z : UInt
+      wire w : UInt
+
+      on-reset r := w
+      when p :
+        on-reset r := x
+        r := a
+      when q :
+        on-reset r := y
+        r := b
+      r := z
+; CHECK: r := Register(mux-uu(reset, mux-uu(q, y, mux-uu(p, x, w)), z), UInt(1))
+; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 45ae938b..de513641 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,15 +3,15 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m : UInt(1)[2]
-      wire i : UInt(1)
-      wire p : UInt(1)
-      wire j : UInt(1)
-      reg r : UInt(1)
+      mem m : UInt<1>[2]
+      wire i : UInt<1>
+      wire p : UInt<1>
+      wire j : UInt<1>
+      reg r : UInt<1>
 
       p := j
       when p :
-        r.init := i
+        on-reset r := i
         accessor a = m[i] 
         i := a
         accessor b = m[i]
@@ -26,7 +26,7 @@ circuit top :
         p := i
         when e :
            p := p
-           r.init := p
+           on-reset r := p
            r := p
         
 
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index 653dfb2d..e5788c11 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : UInt(1)[10]
-      r.init.3 := UInt(0)
+      reg r : UInt<1>[10]
+      on-reset r[3] := UInt(0)
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index c2814038..d3adf5f2 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,13 +3,13 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m :{ x : UInt(1), y : UInt(1) }[2] 
-      wire i : UInt(1)
-      wire p : UInt(1)
-      wire q : { x : UInt(1), y : UInt(1) }
+      mem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      wire i : UInt<1>
+      wire p : UInt<1>
+      wire q : { x : UInt<1>, y : UInt<1> }
       when p :
-        wire p2 : UInt(1)
-        reg r5 : UInt(1)
+        wire p2 : UInt<1>
+        reg r5 : UInt<1>
         when p2 :
           accessor a = m[i] 
           q := a
@@ -21,7 +21,7 @@ circuit top :
           accessor d = m[i]
           d := q
       else :
-        wire p3 : UInt(1)
+        wire p3 : UInt<1>
         when p3 :
           accessor w = m[i] 
           q := w
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index c3d4896a..cde9be6d 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -4,10 +4,9 @@
 circuit top :
    module subtracter :
       wire z : { x : UInt, flip y: SInt}
-      node x = z.x ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt>
-      node y = z.y ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
-
-      wire a : UInt(3)[10] ;CHECK: wire a : UInt(3)[10]@<t:UInt>@<t:UInt(3)[10]@<t:UInt>>
-      node b = a.2 ;CHECK: node b = a@<t:UInt(3)[10]@<t:UInt>>.2@<t:UInt>
-      accessor c = a[UInt(3)] ;CHECK: accessor c = a@<t:UInt(3)[10]@<t:UInt>>[UInt(3)]
+      node x = z.x            ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt>
+      node y = z.y            ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
+      wire a : UInt<3>[10]    ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
+      node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
+      accessor c = a[UInt(3)] ;CHECK: accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)]
 ; CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 300101ad..0b6b19fa 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -9,27 +9,27 @@ circuit top :
       z := sub-wrap(x, y)
       ;CHECK: z@<t:UInt> := sub-wrap-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
 ; CHECK: reg x : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>.z@<t:UInt>
+         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
+         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.z@<t:UInt>
       else :
          inst s2 of subtracter
          s2.x := x
@@ -42,8 +42,8 @@ circuit top :
       ;CHECK: v@<t:UInt> := eq-uu(v@<t:UInt>, UInt(0))@<t:UInt>
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 35634a6f..a17d8f67 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -3,11 +3,11 @@
 ;CHECK: Infer Types
 circuit top :
    module top :
-      wire a : UInt(16)
-      wire b : UInt(8)
-      wire c : SInt(16)
-      wire d : SInt(8)
-      wire e : UInt(1)
+      wire a : UInt<16>
+      wire b : UInt<8>
+      wire c : SInt<16>
+      wire d : SInt<8>
+      wire e : UInt<1>
 
       node vadd = add(a, c)    ;CHECK: node vadd = add-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 864852fb..3cd5c542 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
@@ -8,15 +8,15 @@ circuit top :
       output q : UInt
       q := sub-wrap-uu(x, y)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt-uu(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,8 +33,8 @@ circuit top :
       v := eq-uu(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 50eb5452..0d4dc981 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -3,12 +3,12 @@
 ;CHECK: Infer Widths
 circuit top :
    module top :
-      wire e : UInt(30)
+      wire e : UInt<30>
       reg y : UInt
       y := e
 
-      wire a : UInt(20)
-      wire b : UInt(10)
+      wire a : UInt<20>
+      wire b : UInt<10>
       wire c : UInt
       wire z : UInt
        
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index 8cb856f2..68577431 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -8,15 +8,15 @@ circuit top :
       output q : UInt
       q := sub-wrap-uu(x, y)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt-uu(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,8 +33,8 @@ circuit top :
       v := eq-uu(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 955d44f2..60b62ac7 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -3,43 +3,43 @@
 
 circuit MemorySearch : 
   module MemorySearch : 
-    input target : UInt(4)
-    output address : UInt(3)
-    input en : UInt(1)
-    output done : UInt(1)
+    input target : UInt<4>
+    output address : UInt<3>
+    input en : UInt<1>
+    output done : UInt<1>
     
-    node T_35 = UInt(0, 3)
-    reg index : UInt(3)
-    index.init := T_35
-    node T_36 = UInt(0, 1)
-    node T_37 = UInt(4, 3)
-    node T_38 = UInt(15, 4)
-    node T_39 = UInt(14, 4)
-    node T_40 = UInt(2, 2)
-    node T_41 = UInt(5, 3)
-    node T_42 = UInt(13, 4)
-    wire elts : UInt(1)[7]
-    elts.0 := Pad(T_36,?)
-    elts.1 := Pad(T_37,?)
-    elts.2 := Pad(T_38,?)
-    elts.3 := Pad(T_39,?)
-    elts.4 := Pad(T_40,?)
-    elts.5 := Pad(T_41,?)
-    elts.6 := Pad(T_42,?)
+    node T_35 = UInt<3>(0)
+    reg index : UInt<3>
+    on-reset index := T_35
+    node T_36 = UInt<1>(0)
+    node T_37 = UInt<3>(4)
+    node T_38 = UInt<4>(15)
+    node T_39 = UInt<4>(14)
+    node T_40 = UInt<2>(2)
+    node T_41 = UInt<3>(5)
+    node T_42 = UInt<4>(13)
+    wire elts : UInt<1>[7]
+    elts[0] := Pad(T_36,?)
+    elts[1] := Pad(T_37,?)
+    elts[2] := Pad(T_38,?)
+    elts[3] := Pad(T_39,?)
+    elts[4] := Pad(T_40,?)
+    elts[5] := Pad(T_41,?)
+    elts[6] := Pad(T_42,?)
     accessor elt = elts[index]
     node T_43 = bit-not(en)
     node T_44 = eq(Pad(elt,?), Pad(target,?))
-    node T_45 = UInt(7, 3)
+    node T_45 = UInt<3>(7)
     node T_46 = eq(Pad(index,?), Pad(T_45,?))
     node T_47 = bit-or(T_44, T_46)
     node end = bit-and(T_43, T_47)
     when en : 
-      node T_48 = UInt(0, 1)
+      node T_48 = UInt<1>(0)
       index := Pad(T_48,?)
     else : 
       node T_49 = bit-not(end)
       when T_49 : 
-        node T_50 = UInt(1, 1)
+        node T_50 = UInt<1>(1)
         node T_51 = add-wrap(Pad(index,?), Pad(T_50,?))
         index := Pad(T_51,?)
     done := Pad(end,?)
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 733e2036..832bd279 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,35 +3,35 @@
 
 circuit RegisterVecShift : 
   module RegisterVecShift : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when reset : 
-      node T_38 = UInt(0, 4)
-      node T_39 = UInt(0, 4)
-      node T_40 = UInt(0, 4)
-      node T_41 = UInt(0, 4)
-      wire T_42 : UInt(4)[4]
-      T_42.0 := T_38
-      T_42.1 := T_39
-      T_42.2 := T_40
-      T_42.3 := T_41
+      node T_38 = UInt<4>(0)
+      node T_39 = UInt<4>(0)
+      node T_40 = UInt<4>(0)
+      node T_41 = UInt<4>(0)
+      wire T_42 : UInt<4>[4]
+      T_42[0] := T_38
+      T_42[1] := T_39
+      T_42[2] := T_40
+      T_42[3] := T_41
       delays := T_42
-    node T_43 = UInt(5, 3)
+    node T_43 = UInt<3>(5)
     node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
-    node T_45 = UInt(4, 3)
+    node T_45 = UInt<3>(4)
     node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
     when T_46 : 
-      delays.0 := Pad(ins.0,?)
-      delays.1 := Pad(ins.1,?)
-      delays.2 := Pad(ins.2,?)
-      delays.3 := Pad(ins.3,?)
+      delays[0] := Pad(ins[0],?)
+      delays[1] := Pad(ins[1],?)
+      delays[2] := Pad(ins[2],?)
+      delays[3] := Pad(ins[3],?)
     else : when shift : 
-        delays.0 := Pad(ins.0,?)
-        delays.1 := Pad(delays.0,?)
-        delays.2 := Pad(delays.1,?)
-        delays.3 := Pad(delays.2,?)
-    out := Pad(delays.3,?)
+        delays[0] := Pad(ins[0],?)
+        delays[1] := Pad(delays[0],?)
+        delays[2] := Pad(delays[1],?)
+        delays[3] := Pad(delays[2],?)
+    out := Pad(delays[3],?)
diff --git a/test/passes/jacktest/SIntOps.fir b/test/passes/jacktest/SIntOps.fir
index 45ea68f2..406a09de 100644
--- a/test/passes/jacktest/SIntOps.fir
+++ b/test/passes/jacktest/SIntOps.fir
@@ -3,22 +3,22 @@
 
 circuit SIntOps : 
   module SIntOps : 
-    input b : SInt(16)
-    input a : SInt(16)
-    output addout : SInt(16)
-    output subout : SInt(16)
-    output timesout : SInt(16)
-    output divout : SInt(16)
-    output modout : SInt(16)
-    output lshiftout : SInt(16)
-    output rshiftout : SInt(16)
-    output lessout : UInt(1)
-    output greatout : UInt(1)
-    output eqout : UInt(1)
-    output noteqout : UInt(1)
-    output lesseqout : UInt(1)
-    output greateqout : UInt(1)
-    output negout : SInt(16)
+    input b : SInt<16>
+    input a : SInt<16>
+    output addout : SInt<16>
+    output subout : SInt<16>
+    output timesout : SInt<16>
+    output divout : SInt<16>
+    output modout : SInt<16>
+    output lshiftout : SInt<16>
+    output rshiftout : SInt<16>
+    output lessout : UInt<1>
+    output greatout : UInt<1>
+    output eqout : UInt<1>
+    output noteqout : UInt<1>
+    output lesseqout : UInt<1>
+    output greateqout : UInt<1>
+    output negout : SInt<16>
     
     node T_35 = add-wrap(a, b)
     addout := T_35
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
index 35442ac8..b458ac4a 100644
--- a/test/passes/jacktest/Tlb.fir
+++ b/test/passes/jacktest/Tlb.fir
@@ -2,13 +2,13 @@
 ; CHECK: Done!
 circuit Tbl : 
   module Tbl : 
-    output o : UInt(16)
-    input i : UInt(16)
-    input d : UInt(16)
-    input we : UInt(1)
+    output o : UInt<16>
+    input i : UInt<16>
+    input d : UInt<16>
+    input we : UInt<1>
     
-    mem m : UInt(10)[256]
-    node T_12 = UInt(0, 1)
+    mem m : UInt<10>[256]
+    node T_12 = UInt<1>(0)
     o := Pad(T_12,?)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/passes/jacktest/UIntOps.fir b/test/passes/jacktest/UIntOps.fir
index bb3e6293..e402f22e 100644
--- a/test/passes/jacktest/UIntOps.fir
+++ b/test/passes/jacktest/UIntOps.fir
@@ -3,21 +3,21 @@
 
 circuit UIntOps : 
   module UIntOps : 
-    input b : UInt(16)
-    input a : UInt(16)
-    output addout : UInt(16)
-    output subout : UInt(16)
-    output timesout : UInt(16)
-    output divout : UInt(16)
-    output modout : UInt(16)
-    output lshiftout : UInt(16)
-    output rshiftout : UInt(16)
-    output lessout : UInt(1)
-    output greatout : UInt(1)
-    output eqout : UInt(1)
-    output noteqout : UInt(1)
-    output lesseqout : UInt(1)
-    output greateqout : UInt(1)
+    input b : UInt<16>
+    input a : UInt<16>
+    output addout : UInt<16>
+    output subout : UInt<16>
+    output timesout : UInt<16>
+    output divout : UInt<16>
+    output modout : UInt<16>
+    output lshiftout : UInt<16>
+    output rshiftout : UInt<16>
+    output lessout : UInt<1>
+    output greatout : UInt<1>
+    output eqout : UInt<1>
+    output noteqout : UInt<1>
+    output lesseqout : UInt<1>
+    output greateqout : UInt<1>
     
     node T_31 = add-wrap(a, b)
     addout := T_31
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index 2d97ee8d..4be5bdf9 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -3,14 +3,14 @@
 ;CHECK: To Flo
 circuit GCD : 
   module GCD : 
-    input b : UInt(16)
-    input a : UInt(16)
-    input e : UInt(1)
-    output z : UInt(16)
-    output v : UInt(1)
+    input b : UInt<16>
+    input a : UInt<16>
+    input e : UInt<1>
+    output z : UInt<16>
+    output v : UInt<1>
     
-    reg x : UInt(16)
-    reg y : UInt(16)
+    reg x : UInt<16>
+    reg y : UInt<16>
     node T_17 = gt(x, y)
     when T_17 : 
       node T_18 = sub-wrap(x, y)
@@ -22,7 +22,7 @@ circuit GCD :
       x := a
       y := b
     z := x
-    node T_20 = UInt(0, 1)
+    node T_20 = UInt<1>(0)
     node T_21 = eq(y, Pad(T_20,?))
     v := T_21
 
diff --git a/test/passes/jacktest/gcd2.fir b/test/passes/jacktest/gcd2.fir
index e6700122..e0220ca1 100644
--- a/test/passes/jacktest/gcd2.fir
+++ b/test/passes/jacktest/gcd2.fir
@@ -2,14 +2,14 @@
 ;CHECK: To Flo
 circuit GCD : 
   module GCD : 
-    input b : UInt(16)
-    input a : UInt(16)
-    input e : UInt(1)
-    output z : UInt(16)
-    output v : UInt(1)
+    input b : UInt<16>
+    input a : UInt<16>
+    input e : UInt<1>
+    output z : UInt<16>
+    output v : UInt<1>
     
-    reg x : UInt(16)
-    reg y : UInt(16)
+    reg x : UInt<16>
+    reg y : UInt<16>
     node T_17 = gt(Pad(x,?), Pad(y,?))
     when T_17 : 
       node T_18 = sub-wrap(Pad(x,?), Pad(y,?))
@@ -21,6 +21,6 @@ circuit GCD :
       x := a
       y := b
     z := x
-    node T_20 = UInt(0, 1)
+    node T_20 = UInt<1>(0)
     node T_21 = eq(Pad(y,?), Pad(T_20,?))
     v := T_21
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 0a13e5c0..bb1512d5 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -3,47 +3,47 @@
 
 circuit Risc : 
   module Risc : 
-    output out : UInt(32)
-    output valid : UInt(1)
-    input boot : UInt(1)
-    input isWr : UInt(1)
-    input wrAddr : UInt(8)
-    input wrData : UInt(32)
+    output out : UInt<32>
+    output valid : UInt<1>
+    input boot : UInt<1>
+    input isWr : UInt<1>
+    input wrAddr : UInt<8>
+    input wrData : UInt<32>
     
-    mem file : UInt(32)[256]
-    mem code : UInt(32)[256]
-    node T_51 = UInt(0, 8)
-    reg pc : UInt(8)
-    pc.init := T_51
-    node add_op = UInt(0, 1)
-    node imm_op = UInt(1, 1)
+    mem file : UInt<32>[256]
+    mem code : UInt<32>[256]
+    node T_51 = UInt<8>(0)
+    reg pc : UInt<8>
+    on-reset pc := T_51
+    node add_op = UInt<1>(0)
+    node imm_op = UInt<1>(1)
     accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
-    node T_52 = UInt(0, 1)
+    node T_52 = UInt<1>(0)
     node T_53 = eq(rai, T_52)
-    node T_54 = UInt(0, 1)
+    node T_54 = UInt<1>(0)
     accessor T_55 = file[rai]
     node ra = mux(T_53, T_54, T_55)
-    node T_56 = UInt(0, 1)
+    node T_56 = UInt<1>(0)
     node T_57 = eq(rbi, T_56)
-    node T_58 = UInt(0, 1)
+    node T_58 = UInt<1>(0)
     accessor T_59 = file[rbi]
     node rb = mux(T_57, T_58, T_59)
-    wire rc : UInt(32)
-    node T_60 = UInt(0, 1)
+    wire rc : UInt<32>
+    node T_60 = UInt<1>(0)
     valid := T_60
-    node T_61 = UInt(0, 1)
+    node T_61 = UInt<1>(0)
     out := T_61
-    node T_62 = UInt(0, 1)
+    node T_62 = UInt<1>(0)
     rc := T_62
     when isWr : 
       accessor T_63 = code[wrAddr]
       T_63 := wrData
     else : when boot : 
-        node T_64 = UInt(0, 1)
+        node T_64 = UInt<1>(0)
         pc := T_64
       else : 
         node T_65 = eq(add_op, op)
@@ -56,15 +56,15 @@ circuit Risc :
           node T_69 = bit-or(T_68, rbi)
           rc := T_69
         out := rc
-        node T_70 = UInt(255, 8)
+        node T_70 = UInt<8>(255)
         node T_71 = eq(rci, T_70)
         when T_71 : 
-          node T_72 = UInt(1, 1)
+          node T_72 = UInt<1>(1)
           valid := T_72
         else : 
           accessor T_73 = file[rci]
           T_73 := rc
-        node T_74 = UInt(1, 1)
+        node T_74 = UInt<1>(1)
         node T_75 = add-wrap(pc, T_74)
         pc := T_75
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/testlower.fir b/test/passes/jacktest/testlower.fir
index c338d094..7b096ff3 100644
--- a/test/passes/jacktest/testlower.fir
+++ b/test/passes/jacktest/testlower.fir
@@ -4,17 +4,17 @@
 
 circuit BundleWire : 
   module BundleWire : 
-    input in : { y : UInt(32), x : UInt(32) }
-    output outs : { y : UInt(32), x : UInt(32) }[4]
+    input in : { y : UInt<32>, x : UInt<32> }
+    output outs : { y : UInt<32>, x : UInt<32> }[4]
     
-    wire coords : { y : UInt(32), x : UInt(32) }[4]
-    coords.0 := in
-    outs.0 := coords.0
-    coords.1 := in
-    outs.1 := coords.1
-    coords.2 := in
-    outs.2 := coords.2
-    coords.3 := in
-    outs.3 := coords.3
+    wire coords : { y : UInt<32>, x : UInt<32> }[4]
+    coords[0] := in
+    outs[0] := coords[0]
+    coords[1] := in
+    outs[1] := coords[1]
+    coords[2] := in
+    outs[2] := coords[2]
+    coords[3] := in
+    outs[3] := coords[3]
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir
index 4d2563af..9914ea04 100644
--- a/test/passes/jacktest/vecshift.fir
+++ b/test/passes/jacktest/vecshift.fir
@@ -4,21 +4,21 @@
 
 circuit VecShiftRegister : 
   module VecShiftRegister : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when load : 
-      delays.0 := ins.0
-      delays.1 := ins.1
-      delays.2 := ins.2
-      delays.3 := ins.3
+      delays[0] := ins[0]
+      delays[1] := ins[1]
+      delays[2] := ins[2]
+      delays[3] := ins[3]
      else : when shift : 
-        delays.0 := ins.0
-        delays.1 := delays.0
-        delays.2 := delays.1
-        delays.3 := delays.2
-    out := delays.3
+        delays[0] := ins[0]
+        delays[1] := delays[0]
+        delays[2] := delays[1]
+        delays[3] := delays[2]
+    out := delays[3]
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 0ebbb13d..2b73a8e9 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -3,26 +3,26 @@
 ; CHECK: Lower To Ground
 circuit top :
    module m :
-      wire i : UInt(2)
-      wire j : UInt(32)
+      wire i : UInt<2>
+      wire j : UInt<32>
 
-      wire a : UInt(32)[4]
-      ; CHECK: wire a$0 : UInt(32)
-      ; CHECK: wire a$1 : UInt(32)
-      ; CHECK: wire a$2 : UInt(32)
-      ; CHECK: wire a$3 : UInt(32)
+      wire a : UInt<32>[4]
+      ; CHECK: wire a$0 : UInt<32>
+      ; CHECK: wire a$1 : UInt<32>
+      ; CHECK: wire a$2 : UInt<32>
+      ; CHECK: wire a$3 : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b : UInt(32)
+      ; CHECK: wire b : UInt<32>
       ; CHECK: b := (a$0 a$1 a$2 a$3)[i]
       j := b
 
       accessor c = a[i]
-      ; CHECK: wire c : UInt(32)
+      ; CHECK: wire c : UInt<32>
       ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
       c := j
       
-      mem p : UInt(32)[4]
+      mem p : UInt<32>[4]
       accessor t = p[i]
       ; CHECK: accessor t = p[i]
       j := t
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 77de74db..a4ba1eab 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -6,22 +6,22 @@ circuit top :
       wire i : UInt
       wire j : UInt
 
-      wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a$0$x : UInt(32)
-      ; CHECK: wire a$0$y : UInt(32)
-      ; CHECK: wire a$1$x : UInt(32)
-      ; CHECK: wire a$1$y : UInt(32)
+      wire a : { x : UInt<32>, flip y : UInt<32> }[2]
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b$x : UInt(32)
-      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
       ; CHECK: b$x := (a$0$x a$1$x)[i]
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
       
       accessor c = a[i]
-      ; CHECK: wire c$x : UInt(32)
-      ; CHECK: wire c$y : UInt(32)
+      ; CHECK: wire c$x : UInt<32>
+      ; CHECK: wire c$y : UInt<32>
       ; CHECK: (a$0$x a$1$x)[i] := c$x
       ; CHECK: c$y := (a$0$y a$1$y)[i]
       c := j
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 859ddb47..ca676ba5 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -21,7 +21,7 @@ circuit top :
 ;CHECK:       output a$y : SInt
 ;CHECK:       output b$x : UInt
 ;CHECK:       input b$y : SInt
-;CHECK:       input reset : UInt(1)
+;CHECK:       input reset : UInt<1>
 ;CHECK:    module subtracter :
 ;CHECK:       input c$x$0 : UInt
 ;CHECK:       input c$x$1 : UInt
@@ -32,7 +32,7 @@ circuit top :
 ;CHECK:       output c$y$x$1 : UInt
 ;CHECK:       output c$y$x$2 : UInt
 ;CHECK:       input c$y$y : SInt
-;CHECK:       input reset : UInt(1)
+;CHECK:       input reset : UInt<1>
 ;CHECK:       wire a$x : UInt
 ;CHECK:       wire a$y : SInt
 ;CHECK:       wire b$x : UInt
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 0b14c187..1e9c8f9f 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -4,24 +4,24 @@
 circuit top :
    module q :
       wire i : UInt
-      wire j : { x : UInt(32), flip y : UInt(32) }
+      wire j : { x : UInt<32>, flip y : UInt<32> }
 
-      wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a$0$x : UInt(32)
-      ; CHECK: wire a$0$y : UInt(32)
-      ; CHECK: wire a$1$x : UInt(32)
-      ; CHECK: wire a$1$y : UInt(32)
+      wire a : { x : UInt<32>, flip y : UInt<32> }[2]
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b$x : UInt(32)
-      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
       ; CHECK: b$x := (a$0$x a$1$x)[i]
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: mem m$x : UInt(32)[2]
-      ; CHECK: mem m$y : UInt(32)[2]
+      mem m : { x : UInt<32>, flip y : UInt<32> }[2]
+      ; CHECK: mem m$x : UInt<32>[2]
+      ; CHECK: mem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 23ac8ac3..918710a5 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -3,19 +3,19 @@
 ; CHECK: Lower To Ground
          circuit top :
             module top :
-               input a : UInt(16)
-               input b : UInt(16)
+               input a : UInt<16>
+               input b : UInt<16>
                output z : UInt
 
                reg r1 : { x : UInt, flip y : SInt }
                wire q : { x : UInt, flip y : SInt }
-               r1.init := q    
+               on-reset r1 := q    
 
       ; CHECK: reg r1$x : UInt
       ; CHECK: reg r1$y : SInt
       ; CHECK: wire q$x : UInt
       ; CHECK: wire q$y : SInt
-      ; CHECK: r1$x.init := q$x
-      ; CHECK: q$y := r1$y.init
+      ; CHECK: on-reset r1$x := q$x
+      ; CHECK: on-reset q$y := r1$y   
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir
index 720663c1..a255dc33 100644
--- a/test/passes/make-explicit-reset/mix-reset.fir
+++ b/test/passes/make-explicit-reset/mix-reset.fir
@@ -3,26 +3,26 @@
 ; CHECK: Make Explicit Reset
 circuit top :
    module A :
-      ;CHECK: input reset : UInt(1)
-      input x : UInt(16)
-      output y : UInt(16)
+      ;CHECK: input reset : UInt<1>
+      input x : UInt<16>
+      output y : UInt<16>
       inst b of B
       ;CHECK: b.reset := reset
    module B :
-      input reset : UInt(1)
-      ;CHECK: input reset : UInt(1)
-      input x : UInt(16)
-      output y : UInt(16)
+      input reset : UInt<1>
+      ;CHECK: input reset : UInt<1>
+      input x : UInt<16>
+      output y : UInt<16>
       inst c of C
       ;CHECK: c.reset := reset
    module C :
-      ;CHECK: input reset : UInt(1)
-      input a : UInt(16)
-      input b : UInt(16)
+      ;CHECK: input reset : UInt<1>
+      input a : UInt<16>
+      input b : UInt<16>
    module top :
-      ;CHECK: input reset : UInt(1)
-      input a : UInt(16)
-      input b : UInt(16)
+      ;CHECK: input reset : UInt<1>
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst a of A
       ;CHECK: a.reset := reset
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 931372cb..8cae8ba4 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -3,7 +3,7 @@
 ;CHECK: Resolve Genders
 circuit top :
    module top :
-      wire m : UInt(32)[10][10][10]
+      wire m : UInt<32>[10][10][10]
       wire i : UInt
       accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
       accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
index 48987a9a..56029969 100644
--- a/test/passes/resolve-genders/bigenders.fir
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -3,9 +3,9 @@
 ;CHECK: Resolve Genders
 circuit top :
    module M :
-      input i : UInt(10)
-      output o : UInt(10)
-      wire w : {x : UInt(10), flip y : UInt(10)}
+      input i : UInt<10>
+      output o : UInt<10>
+      wire w : {x : UInt<10>, flip y : UInt<10>}
       w.x := i
       w.y := i
       o := w.x
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir
index 491760b6..9688a71b 100644
--- a/test/passes/resolve-genders/bulk.fir
+++ b/test/passes/resolve-genders/bulk.fir
@@ -3,9 +3,9 @@
 ;CHECK: Resolve Genders
 circuit top :
    module source :
-      output bundle : { data : UInt(16), flip ready : UInt(1) }
+      output bundle : { data : UInt<16>, flip ready : UInt<1> }
    module sink :
-      input bundle : { data : UInt(16), flip ready : UInt(1) }
+      input bundle : { data : UInt<16>, flip ready : UInt<1> }
    module top :
       inst src of source
       inst snk of sink
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 44e0200f..b16c9b66 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -9,16 +9,16 @@ circuit top :
       z := sub-wrap(x, y)
       ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
 ; CHECK: reg x : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
          inst s of subtracter
@@ -40,8 +40,8 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index c1708631..3155dbcf 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -3,14 +3,14 @@
 ;CHECK: Resolve Genders
 circuit top :
    module source :
-      output data : UInt(16)
-      input ready : UInt(1)
+      output data : UInt<16>
+      input ready : UInt<1>
       data := UInt(16)
    module sink :
-      input data : UInt(16)
-      output ready : UInt(1)
+      input data : UInt<16>
+      output ready : UInt<1>
    module top: 
-      wire connect : { data : UInt(16), flip ready: UInt(1) }
+      wire connect : { data : UInt<16>, flip ready: UInt<1> }
       inst src of source         ;CHECK: inst src of source@<g:female>
       inst snk of sink           ;CHECK: inst snk of sink@<g:female>
       connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 77cf13b3..6abc411a 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -3,8 +3,8 @@
 ;CHECK: Lower To Ground
 circuit top :
    module M :
-      wire w : { flip x : UInt(10)}
-      reg r : { flip x : UInt(10)}
+      wire w : { flip x : UInt<10>}
+      reg r : { flip x : UInt<10>}
       w := r     ; CHECK r$x := w$x
       w.x := r.x ; CHECK w$x := r$x
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index 4ad23a6a..10278fdb 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -9,15 +9,15 @@ circuit top :
       z := sub-wrap(x, y)
       ;CHECK: z@<k:port> := sub-wrap(x@<k:port>, y@<k:port>)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -35,8 +35,8 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       ;CHECK: inst i of gcd@<k:module>
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index 75efa2f8..71835204 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -8,15 +8,15 @@ circuit top :
       output q : UInt
       q := sub-wrap-uu(x, y)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt-uu(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,8 +33,8 @@ circuit top :
       v := eq-uu(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
index 9ea5d7b1..c8f2b268 100644
--- a/test/passes/to-flo/gcd.fir
+++ b/test/passes/to-flo/gcd.fir
@@ -8,15 +8,15 @@ circuit top :
       output q : UInt
       q := sub-wrap-uu(x, y)
    module gcd :
-      input a : UInt(16)
-      input b : UInt(16)
-      input e : UInt(1)
-      output z : UInt(16)
-      output v : UInt(1)
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
       reg x : UInt
       reg y : UInt
-      x.init := UInt(0)
-      y.init := UInt(42)
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
       when gt-uu(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,8 +33,8 @@ circuit top :
       v := eq-uu(v, UInt(0))
       z := x
    module top :
-      input a : UInt(16)
-      input b : UInt(16)
+      input a : UInt<16>
+      input b : UInt<16>
       output z : UInt
       inst i of gcd
       i.a := a