merge

2 files changed, 45 insertions, 59 deletions

diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7379024b..a4617267 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -6,25 +6,25 @@ circuit ModuleVec :
     output out : UInt<32>
     
     node T_33 = UInt<1>(1)
-    node T_34 = add(in, T_33)
-    out := T_34
+    node T_34 = add-wrap(Pad(in,?), Pad(T_33,?))
+    out := Pad(T_34,?)
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
     node T_35 = UInt<1>(1)
-    node T_36 = add(in, T_35)
-    out := T_36
+    node T_36 = add-wrap(Pad(in,?), Pad(T_35,?))
+    out := Pad(T_36,?)
   module ModuleVec : 
-    output ins : UInt<32>[2]
+    input ins : UInt<32>[2]
     output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
-    pluses[0] := T_37
-    pluses[1] := T_38
-    pluses.s.in := ins.s
-    outs[0] := pluses.s.out
-    pluses.s.in := ins[1]
-    outs[1] := pluses[1].out
+    wire pluses : { in : UInt<32>, flip out : UInt<32>}[2]
+    pluses[0] := Pad(T_37,?)
+    pluses[1] := Pad(T_38,?)
+    pluses[0].in := Pad(ins[0],?)
+    outs[0] := Pad(pluses[0].out,?)
+    pluses[1].in := Pad(ins[1],?)
+    outs[1] := Pad(pluses[1].out,?)
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index bb1512d5..a73d57c4 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
-; CHECK: Expand Whens
+; CHECK: Done!
 
 circuit Risc : 
   module Risc : 
@@ -12,59 +12,45 @@ circuit Risc :
     
     mem file : UInt<32>[256]
     mem code : UInt<32>[256]
-    node T_51 = UInt<8>(0)
     reg pc : UInt<8>
-    on-reset pc := T_51
-    node add_op = UInt<1>(0)
-    node imm_op = UInt<1>(1)
+    on-reset pc := Pad(UInt<8>(0),?)
     accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
-    node T_52 = UInt<1>(0)
-    node T_53 = eq(rai, T_52)
-    node T_54 = UInt<1>(0)
-    accessor T_55 = file[rai]
-    node ra = mux(T_53, T_54, T_55)
-    node T_56 = UInt<1>(0)
-    node T_57 = eq(rbi, T_56)
-    node T_58 = UInt<1>(0)
-    accessor T_59 = file[rbi]
-    node rb = mux(T_57, T_58, T_59)
+    node T_51 = eq(Pad(rai,?), Pad(UInt<1>(0),?))
+    accessor T_52 = file[rai]
+    node ra = mux(Pad(T_51,?), Pad(UInt<1>(0),?), Pad(T_52,?))
+    node T_53 = eq(Pad(rbi,?), Pad(UInt<1>(0),?))
+    accessor T_54 = file[rbi]
+    node rb = mux(Pad(T_53,?), Pad(UInt<1>(0),?), Pad(T_54,?))
     wire rc : UInt<32>
-    node T_60 = UInt<1>(0)
-    valid := T_60
-    node T_61 = UInt<1>(0)
-    out := T_61
-    node T_62 = UInt<1>(0)
-    rc := T_62
+    node T_55 = UInt<1>(0)
+    valid := Pad(T_55,?)
+    out := Pad(UInt<1>(0),?)
+    rc := Pad(UInt<1>(0),?)
     when isWr : 
-      accessor T_63 = code[wrAddr]
-      T_63 := wrData
-    else : when boot : 
-        node T_64 = UInt<1>(0)
-        pc := T_64
+      accessor T_56 = code[wrAddr]
+      T_56 := Pad(wrData,?)
+    else : when boot : pc := Pad(UInt<1>(0),?)
       else : 
-        node T_65 = eq(add_op, op)
-        when T_65 : 
-          node T_66 = add-wrap(ra, rb)
-          rc := T_66
-        node T_67 = eq(imm_op, op)
-        when T_67 : 
-          node T_68 = shl(rai, 8)
-          node T_69 = bit-or(T_68, rbi)
-          rc := T_69
-        out := rc
-        node T_70 = UInt<8>(255)
-        node T_71 = eq(rci, T_70)
-        when T_71 : 
-          node T_72 = UInt<1>(1)
-          valid := T_72
+        node T_57 = eq(Pad(UInt<1>(0),?), Pad(op,?))
+        when T_57 : 
+          node T_58 = add-wrap(Pad(ra,?), Pad(rb,?))
+          rc := Pad(T_58,?)
+        node T_59 = eq(Pad(UInt<1>(1),?), Pad(op,?))
+        when T_59 : 
+          node T_60 = shl(rai, 8)
+          node T_61 = bit-or(Pad(T_60,?), Pad(rbi,?))
+          rc := Pad(T_61,?)
+        out := Pad(rc,?)
+        node T_62 = eq(Pad(rci,?), Pad(UInt<8>(255),?))
+        when T_62 : 
+          node T_63 = UInt<1>(1)
+          valid := Pad(T_63,?)
         else : 
-          accessor T_73 = file[rci]
-          T_73 := rc
-        node T_74 = UInt<1>(1)
-        node T_75 = add-wrap(pc, T_74)
-        pc := T_75
-; CHECK: Finished Expand Whens
+          accessor T_64 = file[rci]
+          T_64 := Pad(rc,?)
+        node T_65 = add-wrap(Pad(pc,?), Pad(UInt<1>(1),?))
+        pc := Pad(T_65,?)