diff options
| author | azidar | 2015-06-03 20:39:41 -0700 |
|---|---|---|
| committer | azidar | 2015-06-03 20:39:41 -0700 |
| commit | 887d785ecc2ba7c363194cef89b72bc026c81cf9 (patch) | |
| tree | 350224acd106b5e5a4bbfccef793ac412a86b556 /test/riscv-mini/Core.fir | |
| parent | 0a0c2d7c13c5beaa7c5132963112cc9e747ff287 (diff) | |
Fixed verilog backend bugs. Passes ALU. Fails Datapath
Diffstat (limited to 'test/riscv-mini/Core.fir')
| -rw-r--r-- | test/riscv-mini/Core.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/riscv-mini/Core.fir b/test/riscv-mini/Core.fir index eaa5697e..aea05940 100644 --- a/test/riscv-mini/Core.fir +++ b/test/riscv-mini/Core.fir @@ -12,7 +12,7 @@ circuit Core : node shamt = bits(B, 4, 0) node T_1224 = add-wrap(A, B) node T_1225 = sub-wrap(A, B) - node T_1226 = convert(A) + node T_1226 = as-SInt(A) node T_1227 = dshr(T_1226, shamt) node T_1228 = as-UInt(T_1227) node T_1229 = dshr(A, shamt) |