From 887d785ecc2ba7c363194cef89b72bc026c81cf9 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 3 Jun 2015 20:39:41 -0700
Subject: Fixed verilog backend bugs. Passes ALU. Fails Datapath

---
 test/riscv-mini/Core.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/riscv-mini/Core.fir')

diff --git a/test/riscv-mini/Core.fir b/test/riscv-mini/Core.fir
index eaa5697e..aea05940 100644
--- a/test/riscv-mini/Core.fir
+++ b/test/riscv-mini/Core.fir
@@ -12,7 +12,7 @@ circuit Core :
     node shamt = bits(B, 4, 0)
     node T_1224 = add-wrap(A, B)
     node T_1225 = sub-wrap(A, B)
-    node T_1226 = convert(A)
+    node T_1226 = as-SInt(A)
     node T_1227 = dshr(T_1226, shamt)
     node T_1228 = as-UInt(T_1227)
     node T_1229 = dshr(A, shamt)
-- 
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