diff options
| author | azidar | 2016-01-27 14:18:09 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 2428d391d02a9ff413884e073ae3e6ac37f2df2d (patch) | |
| tree | a433fca39129f2642a599643002da66299482aaa /test/passes/split-exp | |
| parent | 067eb9db57f6c9f5f3675d9be11133378531a9b5 (diff) | |
Added addw to working ir as an optimized verilog emission
Diffstat (limited to 'test/passes/split-exp')
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 06d1463d..207ad757 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -14,16 +14,12 @@ circuit Top : when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) -;CHECK: node GEN_0 = sub(a, c) -;CHECK: node GEN_1 = tail(GEN_0, 1) -;CHECK: node GEN_2 = bits(GEN_1, 3, 3) -;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd")) -;CHECK: node GEN_4 = add(b, c) -;CHECK: node GEN_5 = tail(GEN_4, 1) -;CHECK: node GEN_6 = add(a, GEN_5) -;CHECK: node GEN_7 = tail(GEN_6, 1) -;CHECK: node GEN_8 = sub(c, b) -;CHECK: node GEN_9 = tail(GEN_8, 1) -;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out) +;CHECK: node GEN_0 = subw(a, c) +;CHECK: node GEN_1 = bits(GEN_0, 3, 3) +;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd")) +;CHECK: node GEN_3 = addw(b, c) +;CHECK: node GEN_4 = addw(a, GEN_3) +;CHECK: node GEN_5 = subw(c, b) +;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out) ;CHECK: Finished Split Expressions |