diff options
| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/passes/split-exp/split-in-when.fir | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/passes/split-exp/split-in-when.fir')
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index e4d0da36..207ad757 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -9,13 +9,14 @@ circuit Top : input b : UInt<10> input c : UInt<10> - reg out : UInt<10>,clk,p,a + reg out : UInt<10>,clk with : + reset => (p,a) - when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) + when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) ;CHECK: node GEN_0 = subw(a, c) -;CHECK: node GEN_1 = bit(GEN_0, 3) -;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd")) +;CHECK: node GEN_1 = bits(GEN_0, 3, 3) +;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd")) ;CHECK: node GEN_3 = addw(b, c) ;CHECK: node GEN_4 = addw(a, GEN_3) ;CHECK: node GEN_5 = subw(c, b) |