From 5ab30c681558d2a26000696e518ee5b28deb1303 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:18:34 -0800
Subject: Updated all tests to pass

---
 test/passes/split-exp/split-in-when.fir | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

(limited to 'test/passes/split-exp/split-in-when.fir')

diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index e4d0da36..06d1463d 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -9,16 +9,21 @@ circuit Top :
       input b : UInt<10>
       input c : UInt<10>
       
-      reg out : UInt<10>,clk,p,a
+      reg out : UInt<10>,clk with :
+         reset => (p,a)
 
-      when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
+      when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
 
-;CHECK: node GEN_0 = subw(a, c)
-;CHECK: node GEN_1 = bit(GEN_0, 3)
-;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd"))
-;CHECK: node GEN_3 = addw(b, c)
-;CHECK: node GEN_4 = addw(a, GEN_3)
-;CHECK: node GEN_5 = subw(c, b)
-;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)   
+;CHECK: node GEN_0 = sub(a, c)
+;CHECK: node GEN_1 = tail(GEN_0, 1)
+;CHECK: node GEN_2 = bits(GEN_1, 3, 3)
+;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_4 = add(b, c)
+;CHECK: node GEN_5 = tail(GEN_4, 1)
+;CHECK: node GEN_6 = add(a, GEN_5)
+;CHECK: node GEN_7 = tail(GEN_6, 1)
+;CHECK: node GEN_8 = sub(c, b)
+;CHECK: node GEN_9 = tail(GEN_8, 1)
+;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out)   
 
 ;CHECK: Finished Split Expressions
-- 
cgit v1.2.3


From 2428d391d02a9ff413884e073ae3e6ac37f2df2d Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 14:18:09 -0800
Subject: Added addw to working ir as an optimized verilog emission

---
 test/passes/split-exp/split-in-when.fir | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

(limited to 'test/passes/split-exp/split-in-when.fir')

diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index 06d1463d..207ad757 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -14,16 +14,12 @@ circuit Top :
 
       when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
 
-;CHECK: node GEN_0 = sub(a, c)
-;CHECK: node GEN_1 = tail(GEN_0, 1)
-;CHECK: node GEN_2 = bits(GEN_1, 3, 3)
-;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd"))
-;CHECK: node GEN_4 = add(b, c)
-;CHECK: node GEN_5 = tail(GEN_4, 1)
-;CHECK: node GEN_6 = add(a, GEN_5)
-;CHECK: node GEN_7 = tail(GEN_6, 1)
-;CHECK: node GEN_8 = sub(c, b)
-;CHECK: node GEN_9 = tail(GEN_8, 1)
-;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out)   
+;CHECK: node GEN_0 = subw(a, c)
+;CHECK: node GEN_1 = bits(GEN_0, 3, 3)
+;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_3 = addw(b, c)
+;CHECK: node GEN_4 = addw(a, GEN_3)
+;CHECK: node GEN_5 = subw(c, b)
+;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)   
 
 ;CHECK: Finished Split Expressions
-- 
cgit v1.2.3