New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

7 files changed, 65 insertions, 65 deletions

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 4d816238..64797ece 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -4,31 +4,31 @@
 circuit top :
    module top :
       wire m : UInt<32>[2][2][2]
-      m[0][0][0] := UInt(1)
-      m[1][0][0] := UInt(1)
-      m[0][1][0] := UInt(1)
-      m[1][1][0] := UInt(1)
-      m[0][0][1] := UInt(1)
-      m[1][0][1] := UInt(1)
-      m[0][1][1] := UInt(1)
-      m[1][1][1] := UInt(1)
+      m[0][0][0] <= UInt(1)
+      m[1][0][0] <= UInt(1)
+      m[0][1][0] <= UInt(1)
+      m[1][1][0] <= UInt(1)
+      m[0][0][1] <= UInt(1)
+      m[1][0][1] <= UInt(1)
+      m[0][1][1] <= UInt(1)
+      m[1][1][1] <= UInt(1)
       wire i : UInt
-      i := UInt(1)
+      i <= UInt(1)
       infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
       infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
       infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
       wire j : UInt
-      j := c
+      j <= c
 
       infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
-      x[0][0] := UInt(1)
-      x[1][0] := UInt(1)
-      x[0][1] := UInt(1)
-      x[1][1] := UInt(1)
+      x[0][0] <= UInt(1)
+      x[1][0] <= UInt(1)
+      x[0][1] <= UInt(1)
+      x[1][1] <= UInt(1)
       infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
-      y[0] := UInt(1)
-      y[1] := UInt(1)
+      y[0] <= UInt(1)
+      y[1] <= UInt(1)
       infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
-      z := j
+      z <= j
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
index 7bdd707c..a13390f7 100644
--- a/test/passes/resolve-genders/bigenders.fir
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -6,8 +6,8 @@ circuit top :
       input i : UInt<10>
       output o : UInt<10>
       wire w : {x : UInt<10>, flip y : UInt<10>}
-      w.x := i
-      w.y := i
-      o := w.x
-      o := w.y
+      w.x <= i
+      w.y <= i
+      o <= w.x
+      o <= w.y
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir
index 193758ec..7e746a37 100644
--- a/test/passes/resolve-genders/bulk.fir
+++ b/test/passes/resolve-genders/bulk.fir
@@ -9,6 +9,6 @@ circuit top :
    module top :
       inst src of source
       inst snk of sink
-      snk.bundle := src.bundle
+      snk.bundle <= src.bundle
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 70556474..85b6474b 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z := subw(x, y)
-      ;CHECK: z@<g:f> := subw(x@<g:m>, y@<g:m>)
+      z <= subw(x, y)
+      ;CHECK: z@<g:f> <= subw(x@<g:m>, y@<g:m>)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -19,28 +19,28 @@ circuit top :
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
 ; CHECK: reg x : UInt
-      onreset x := UInt(0)
-      onreset y := UInt(42)
+      onreset x <= UInt(0)
+      onreset y <= UInt(42)
       when gt(x, y) :
       ;CHECK: when gt(x@<g:m>, y@<g:m>) :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<g:m>
-         s.x := x
-         s.y := y
-         x := s.z
-         ;CHECK: s@<g:m>.x@<g:f> := x@<g:m>
-         ;CHECK: s@<g:m>.y@<g:f> := y@<g:m>
-         ;CHECK: x@<g:f> := s@<g:m>.z@<g:m>
+         s.x <= x
+         s.y <= y
+         x <= s.z
+         ;CHECK: s@<g:m>.x@<g:f> <= x@<g:m>
+         ;CHECK: s@<g:m>.y@<g:f> <= y@<g:m>
+         ;CHECK: x@<g:f> <= s@<g:m>.z@<g:m>
       else :
          inst s2 of subtracter
-         s2.x := x
-         s2.y := y
-         y := s2.z
+         s2.x <= x
+         s2.y <= y
+         y <= s2.z
       when e :
-         x := a
-         y := b
-      v := eq(v, UInt(0))
-      z := x
+         x <= a
+         y <= b
+      v <= eq(v, UInt(0))
+      z <= x
    module top :
       input clk : Clock
       input reset : UInt<1>
@@ -48,11 +48,11 @@ circuit top :
       input b : UInt<16>
       output z : UInt
       inst i of gcd
-      i.a := a
-      i.b := b
-      i.clk := clk
-      i.reset := reset
-      i.e := UInt(1)
-      z := i.z
+      i.a <= a
+      i.b <= b
+      i.clk <= clk
+      i.reset <= reset
+      i.e <= UInt(1)
+      z <= i.z
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 88eb1000..57c8721d 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -5,7 +5,7 @@ circuit top :
    module source :
       output data : UInt<16>
       input ready : UInt<1>
-      data := UInt(16)
+      data <= UInt(16)
    module sink :
       input data : UInt<16>
       output ready : UInt<1>
@@ -13,9 +13,9 @@ circuit top :
       wire connect : { data : UInt<16>, flip ready: UInt<1> }
       inst src of source         ;CHECK: inst src of source@<g:m>
       inst snk of sink           ;CHECK: inst snk of sink@<g:m>
-      connect.data := src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
-      src.ready := connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
-      snk.data := connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
-      connect.ready := snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
+      connect.data <= src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
+      src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
+      snk.data <= connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
+      connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/rdwraccessor.fir b/test/passes/resolve-genders/rdwraccessor.fir
index 238cfa80..35f88071 100644
--- a/test/passes/resolve-genders/rdwraccessor.fir
+++ b/test/passes/resolve-genders/rdwraccessor.fir
@@ -4,28 +4,28 @@
 circuit top :
    module top :
       wire m : UInt<32>[2][2][2]
-      m[0][0][0] := UInt(1)
-      m[1][0][0] := UInt(1)
-      m[0][1][0] := UInt(1)
-      m[1][1][0] := UInt(1)
-      m[0][0][1] := UInt(1)
-      m[1][0][1] := UInt(1)
-      m[0][1][1] := UInt(1)
-      m[1][1][1] := UInt(1)
+      m[0][0][0] <= UInt(1)
+      m[1][0][0] <= UInt(1)
+      m[0][1][0] <= UInt(1)
+      m[1][1][0] <= UInt(1)
+      m[0][0][1] <= UInt(1)
+      m[1][0][1] <= UInt(1)
+      m[0][1][1] <= UInt(1)
+      m[1][1][1] <= UInt(1)
       wire i : UInt
-      i := UInt(1)
+      i <= UInt(1)
       rdwr accessor a = m[i] ;CHECK: accessor a = m@<g:b>[i@<g:m>]@<g:b>
       rdwr accessor b = a[i] ;CHECK: accessor b = a@<g:b>[i@<g:m>]@<g:b>
       rdwr accessor c = b[i] ;CHECK: accessor c = b@<g:b>[i@<g:m>]@<g:b>
       wire j : UInt
-      j := c
-      c := j
+      j <= c
+      c <= j
 
       rdwr accessor x = m[i] ;CHECK: accessor x = m@<g:b>[i@<g:m>]@<g:b>
       rdwr accessor y = x[i] ;CHECK: accessor y = x@<g:b>[i@<g:m>]@<g:b>
       rdwr accessor z = y[i] ;CHECK: accessor z = y@<g:b>[i@<g:m>]@<g:b>
-      z := j
-      j := z
+      z <= j
+      j <= z
 
 ; CHECK: Finished Resolve Genders
 ; CHECK: Done!
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 9df4b058..f734d08b 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -7,7 +7,7 @@ circuit top :
       input reset : UInt<1>
       wire w : { flip x : UInt<10>}
       reg r : { flip x : UInt<10>},clk,reset
-      w := r     ; CHECK r$x := w$x
-      w.x := r.x ; CHECK w$x := r$x
+      w <= r     ; CHECK r$x := w$x
+      w.x <= r.x ; CHECK w$x := r$x
 ; CHECK: Finished Lower To Ground