diff options
| author | azidar | 2015-08-24 11:45:37 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 11:45:37 -0700 |
| commit | 5d3061bfed8445370e6fa97ec9238ba49e8fafbc (patch) | |
| tree | ba0373c05118215fa332c9e7cd10233a69800f53 /test/passes/resolve-genders | |
| parent | 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 (diff) | |
Changed all tests to use verilog backend.
Diffstat (limited to 'test/passes/resolve-genders')
| -rw-r--r-- | test/passes/resolve-genders/accessor.fir | 2 | ||||
| -rw-r--r-- | test/passes/resolve-genders/bigenders.fir | 2 | ||||
| -rw-r--r-- | test/passes/resolve-genders/bulk.fir | 2 | ||||
| -rw-r--r-- | test/passes/resolve-genders/gcd.fir | 2 | ||||
| -rw-r--r-- | test/passes/resolve-genders/ports.fir | 2 | ||||
| -rw-r--r-- | test/passes/resolve-genders/subbundle.fir | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index 356d494a..4d816238 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index c16949a6..7bdd707c 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 034c9b48..193758ec 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 6b2ea41a..70556474 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index 16c4e30b..88eb1000 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 1fa046c6..9df4b058 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Lower To Ground circuit top : |