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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-14 11:29:55 -0700
commit271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch)
tree8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/resolve-genders
parent0bfb3618b654a4082cc2780887b3ca32e374f455 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/resolve-genders')
-rw-r--r--test/passes/resolve-genders/gcd.fir18
-rw-r--r--test/passes/resolve-genders/subbundle.fir4
2 files changed, 15 insertions, 7 deletions
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 6fbaad85..da15cb78 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -6,19 +6,21 @@ circuit top :
input x : UInt
input y : UInt
output z : UInt
- z := sub-wrap(x, y)
- ;CHECK: z@<g:f> := sub-wrap(x@<g:m>, y@<g:m>)
+ z := subw(x, y)
+ ;CHECK: z@<g:f> := subw(x@<g:m>, y@<g:m>)
module gcd :
input a : UInt<16>
input b : UInt<16>
input e : UInt<1>
+ input clk : Clock
+ input reset : UInt<1>
output z : UInt<16>
output v : UInt<1>
- reg x : UInt
- reg y : UInt
+ reg x : UInt,clk,reset
+ reg y : UInt,clk,reset
; CHECK: reg x : UInt
- on-reset x := UInt(0)
- on-reset y := UInt(42)
+ onreset x := UInt(0)
+ onreset y := UInt(42)
when gt(x, y) :
;CHECK: when gt(x@<g:m>, y@<g:m>) :
inst s of subtracter
@@ -40,12 +42,16 @@ circuit top :
v := eq(v, UInt(0))
z := x
module top :
+ input clk : Clock
+ input reset : UInt<1>
input a : UInt<16>
input b : UInt<16>
output z : UInt
inst i of gcd
i.a := a
i.b := b
+ i.clk := clk
+ i.reset := reset
i.e := UInt(1)
z := i.z
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 383c2a31..354545fb 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -3,8 +3,10 @@
;CHECK: Lower To Ground
circuit top :
module top :
+ input clk : Clock
+ input reset : UInt<1>
wire w : { flip x : UInt<10>}
- reg r : { flip x : UInt<10>}
+ reg r : { flip x : UInt<10>},clk,reset
w := r ; CHECK r$x := w$x
w.x := r.x ; CHECK w$x := r$x
; CHECK: Finished Lower To Ground