diff options
| author | azidar | 2016-01-31 12:59:31 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | e985d47312458459e9ebe42fe99b5a063c08e637 (patch) | |
| tree | d726c711e86d6e948a220a568dcae0a997629d18 /test/passes/remove-accesses/simple3.fir | |
| parent | 2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff) | |
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/remove-accesses/simple3.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple3.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir index 6305e0c9..9aa0f34f 100644 --- a/test/passes/remove-accesses/simple3.fir +++ b/test/passes/remove-accesses/simple3.fir @@ -13,8 +13,8 @@ circuit top : a <= in ;CHECK: wire GEN_0 : UInt<32> -;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0 -;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0 +;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0 +;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0 ;CHECK: GEN_0 <= a ;CHECK: Finished Remove Accesses |