From e985d47312458459e9ebe42fe99b5a063c08e637 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sun, 31 Jan 2016 12:59:31 -0800
Subject: Changed stanza output of UInt/SInt to include widths. Made tests
 match accordingly

---
 test/passes/remove-accesses/simple3.fir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/passes/remove-accesses/simple3.fir')

diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
index 6305e0c9..9aa0f34f 100644
--- a/test/passes/remove-accesses/simple3.fir
+++ b/test/passes/remove-accesses/simple3.fir
@@ -13,8 +13,8 @@ circuit top :
       a <= in
 
 ;CHECK: wire GEN_0 : UInt<32>
-;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0
-;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0
+;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0
+;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0
 ;CHECK: GEN_0 <= a
 
 ;CHECK: Finished Remove Accesses
-- 
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