Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

13 files changed, 84 insertions, 65 deletions

diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index 562787a4..bc803e97 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -9,23 +9,23 @@ circuit ALUTop :
     input alu_op : UInt<4>
     
     node shamt = bits(B, 4, 0)
-    node T_157 = add-wrap(A, B)
-    node T_158 = sub-wrap(A, B)
-    node T_159 = convert(A)
+    node T_157 = addw(A, B)
+    node T_158 = subw(A, B)
+    node T_159 = cvt(A)
     node T_160 = dshr(T_159, shamt)
-    node T_161 = as-UInt(T_160)
+    node T_161 = asUInt(T_160)
     node T_162 = dshr(A, shamt)
     node T_163 = dshl(A, shamt)
     node T_164 = bits(T_163, 31, 0)
-    node T_165 = convert(A)
-    node T_166 = convert(B)
+    node T_165 = cvt(A)
+    node T_166 = cvt(B)
     node T_167 = lt(T_165, T_166)
-    node T_168 = as-UInt(T_167)
+    node T_168 = asUInt(T_167)
     node T_169 = lt(A, B)
-    node T_170 = as-UInt(T_169)
-    node T_171 = bit-and(A, B)
-    node T_172 = bit-or(A, B)
-    node T_173 = bit-xor(A, B)
+    node T_170 = asUInt(T_169)
+    node T_171 = and(A, B)
+    node T_172 = or(A, B)
+    node T_173 = xor(A, B)
     node T_174 = eq(UInt<4>(10), alu_op)
     node T_175 = mux(T_174, A, B)
     node T_176 = eq(UInt<4>(4), alu_op)
@@ -51,9 +51,9 @@ circuit ALUTop :
     node T_195 = bits(oot, 31, 0)
     out := T_195
     node T_196 = bit(alu_op, 0)
-    node T_197 = sub-wrap(UInt<1>(0), B)
+    node T_197 = subw(UInt<1>(0), B)
     node T_198 = mux(T_196, T_197, B)
-    node T_199 = add-wrap(A, T_198)
+    node T_199 = addw(A, T_198)
     sum := T_199
   module ALUdec : 
     input opcode : UInt<7>
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index 48af58b8..65efb47f 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -3,13 +3,15 @@
 circuit Counter : 
   module Counter : 
     input inc : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output tot : UInt<8>
     input amt : UInt<4>
     
-    reg T_13 : UInt<8>
-    on-reset T_13 := UInt<8>(0)
+    reg T_13 : UInt<8>,clk,reset
+    onreset T_13 := UInt<8>(0)
     when inc : 
-      node T_14 = add-wrap(T_13, amt)
+      node T_14 = addw(T_13, amt)
       node T_15 = gt(T_14, UInt<8>(255))
       node T_16 = mux(T_15, UInt<1>(0), T_14)
       T_13 := T_16
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index b9da2273..4e0387d0 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -3,17 +3,19 @@
 circuit EnableShiftRegister : 
   module EnableShiftRegister : 
     input in : UInt<4>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     
-    reg r0 : UInt<4>
-    on-reset r0 := UInt<4>(0)
-    reg r1 : UInt<4>
-    on-reset r1 := UInt<4>(0)
-    reg r2 : UInt<4>
-    on-reset r2 := UInt<4>(0)
-    reg r3 : UInt<4>
-    on-reset r3 := UInt<4>(0)
+    reg r0 : UInt<4>,clk,reset
+    onreset r0 := UInt<4>(0)
+    reg r1 : UInt<4>,clk,reset
+    onreset r1 := UInt<4>(0)
+    reg r2 : UInt<4>,clk,reset
+    onreset r2 := UInt<4>(0)
+    reg r3 : UInt<4>,clk,reset
+    onreset r3 := UInt<4>(0)
     when shift : 
       r0 := in
       r1 := r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index f45002f5..9baa05a6 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -4,17 +4,19 @@ circuit LFSR16 :
   module LFSR16 : 
     output out : UInt<16>
     input inc : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     
-    reg res : UInt<16>
-    on-reset res := UInt<16>(1)
+    reg res : UInt<16>,clk,reset
+    onreset res := UInt<16>(1)
     when inc : 
       node T_16 = bit(res, 0)
       node T_17 = bit(res, 2)
-      node T_18 = bit-xor(T_16, T_17)
+      node T_18 = xor(T_16, T_17)
       node T_19 = bit(res, 3)
-      node T_20 = bit-xor(T_18, T_19)
+      node T_20 = xor(T_18, T_19)
       node T_21 = bit(res, 5)
-      node T_22 = bit-xor(T_20, T_21)
+      node T_22 = xor(T_20, T_21)
       node T_23 = bits(res, 15, 1)
       node T_24 = cat(T_22, T_23)
       res := T_24
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 59352162..ca530ea2 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -5,10 +5,12 @@ circuit MemorySearch :
     input target : UInt<4>
     output address : UInt<3>
     input en : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output done : UInt<1>
     
-    reg index : UInt<3>
-    on-reset index := UInt<3>(0)
+    reg index : UInt<3>,clk,reset
+    onreset index := UInt<3>(0)
     wire elts : UInt<4>[7]
     elts[0] := UInt<4>(0)
     elts[1] := UInt<4>(4)
@@ -18,16 +20,16 @@ circuit MemorySearch :
     elts[5] := UInt<4>(5)
     elts[6] := UInt<4>(13)
     infer accessor elt = elts[index]
-    node T_35 = bit-not(en)
+    node T_35 = not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
-    node T_38 = bit-or(T_36, T_37)
-    node end = bit-and(T_35, T_38)
+    node T_38 = or(T_36, T_37)
+    node end = and(T_35, T_38)
     when en : index := UInt<1>(0)
     else : 
-      node T_39 = bit-not(end)
+      node T_39 = not(end)
       when T_39 : 
-        node T_40 = add-wrap(index, UInt<1>(1))
+        node T_40 = addw(index, UInt<1>(1))
         index := T_40
     done := end
     address := index
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 04c119a1..2fde69f3 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = add-wrap(in, UInt<1>(1))
+    node T_33 = addw(in, UInt<1>(1))
     out := T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_34 = add-wrap(in, UInt<1>(1))
+    node T_34 = addw(in, UInt<1>(1))
     out := T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 14db8769..1552e959 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -24,6 +24,6 @@ circuit Mul :
     tbl[14] := UInt<4>(6)
     tbl[15] := UInt<4>(9)
     node T_42 = shl(x, 2)
-    node T_43 = bit-or(T_42, y)
+    node T_43 = or(T_42, y)
     infer accessor T_44 = tbl[T_43]
     z := T_44
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index d24bc383..cca645d1 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,11 +3,13 @@
 circuit RegisterVecShift : 
   module RegisterVecShift : 
     input load : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4]
+    reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] := UInt<4>(0)
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 4bce2bd4..5bbec6d2 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -5,31 +5,33 @@ circuit Stack :
     input push : UInt<1>
     input pop : UInt<1>
     input en : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    cmem stack_mem : UInt<32>[16]
-    reg sp : UInt<5>
-    on-reset sp := UInt<5>(0)
-    reg out : UInt<32>
-    on-reset out := UInt<32>(0)
+    cmem stack_mem : UInt<32>[16],clk
+    reg sp : UInt<5>,clk,reset
+    onreset sp := UInt<5>(0)
+    reg out : UInt<32>,clk,reset
+    onreset out := UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
-      node T_31 = bit-and(push, T_30)
+      node T_31 = and(push, T_30)
       when T_31 : 
         infer accessor T_32 = stack_mem[sp]
         T_32 := dataIn
-        node T_33 = add-wrap(sp, UInt<1>(1))
+        node T_33 = addw(sp, UInt<1>(1))
         sp := T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
-        node T_35 = bit-and(pop, T_34)
+        node T_35 = and(pop, T_34)
         when T_35 : 
-          node T_36 = sub-wrap(sp, UInt<1>(1))
+          node T_36 = subw(sp, UInt<1>(1))
           sp := T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
-        node T_38 = sub-wrap(sp, UInt<1>(1))
+        node T_38 = subw(sp, UInt<1>(1))
         infer accessor T_39 = stack_mem[T_38]
         out := T_39
     dataOut := out
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index f315aaa9..b916e0f0 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -4,10 +4,11 @@ circuit Tbl :
   module Tbl : 
     input i : UInt<16>
     input d : UInt<16>
+    input clk : Clock
     output o : UInt<16>
     input we : UInt<1>
     
-    cmem m : UInt<10>[256]
+    cmem m : UInt<10>[256],clk
     o := UInt<1>(0)
     when we : 
       infer accessor T_13 = m[i]
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 10784964..0f4bf941 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -5,9 +5,11 @@ circuit VendingMachine :
     output valid : UInt<1>
     input nickel : UInt<1>
     input dime : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     
-    reg state : UInt<3>
-    on-reset state := UInt<3>(0)
+    reg state : UInt<3>,clk,reset
+    onreset state := UInt<3>(0)
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
       when nickel : state := UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index a0c1e10a..f3f12017 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -3,19 +3,21 @@
 circuit GCD : 
   module GCD : 
     input e : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output z : UInt<16>
     output v : UInt<1>
     input a : UInt<16>
     input b : UInt<16>
     
-    reg x : UInt<16>
-    reg y : UInt<16>
+    reg x : UInt<16>,clk,reset
+    reg y : UInt<16>,clk,reset
     node T_17 = gt(x, y)
     when T_17 : 
-      node T_18 = sub-wrap(x, y)
+      node T_18 = subw(x, y)
       x := T_18
     else : 
-      node T_19 = sub-wrap(y, x)
+      node T_19 = subw(y, x)
       y := T_19
     when e : 
       x := a
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 21030448..fda21820 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
+; CHECK: Done!
 circuit Risc : 
   module Risc : 
     output out : UInt<32>
@@ -8,11 +8,13 @@ circuit Risc :
     input isWr : UInt<1>
     input wrAddr : UInt<8>
     input wrData : UInt<32>
+    input clk : Clock
+    input reset : UInt<1>
     
-    cmem file : UInt<32>[256]
-    cmem code : UInt<32>[256]
-    reg pc : UInt<8>
-    on-reset pc := UInt<8>(0)
+    cmem file : UInt<32>[256],clk
+    cmem code : UInt<32>[256],clk
+    reg pc : UInt<8>,clk,reset
+    onreset pc := UInt<8>(0)
     infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
@@ -35,12 +37,12 @@ circuit Risc :
       else : 
         node T_56 = eq(UInt<1>(0), op)
         when T_56 : 
-          node T_57 = add-wrap(ra, rb)
+          node T_57 = addw(ra, rb)
           rc := T_57
         node T_58 = eq(UInt<1>(1), op)
         when T_58 : 
           node T_59 = shl(rai, 8)
-          node T_60 = bit-or(T_59, rbi)
+          node T_60 = or(T_59, rbi)
           rc := T_60
         out := rc
         node T_61 = eq(rci, UInt<8>(255))
@@ -48,5 +50,5 @@ circuit Risc :
         else : 
           infer accessor T_62 = file[rci]
           T_62 := rc
-        node T_63 = add-wrap(pc, UInt<1>(1))
+        node T_63 = addw(pc, UInt<1>(1))
         pc := T_63