diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch) | |
| tree | 8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/expand-whens/bundle-init.fir | |
| parent | 0bfb3618b654a4082cc2780887b3ca32e374f455 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/expand-whens/bundle-init.fir')
| -rw-r--r-- | test/passes/expand-whens/bundle-init.fir | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 261ebf02..10da47cf 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -2,7 +2,9 @@ ; CHECK: Expand Whens circuit top : module top : - reg r : { x : UInt, flip y : UInt} + input clk : Clock + input reset : UInt<1> + reg r : { x : UInt, flip y : UInt},clk,reset wire a : UInt wire b : UInt wire w : { x : UInt, flip y : UInt} @@ -13,7 +15,7 @@ circuit top : w.y := a r.x := a r.y := b - on-reset r := w + onreset r := w ; CHECK: when UInt(1) : r$x := mux(reset, w$x, a) ; CHECK: when UInt(1) : r$y := b |