From 271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 13 Jul 2015 16:22:43 -0700
Subject: Added tests for clocks. Added remove scope and special chars passes.
 Added tests. Made more tests pass

---
 test/passes/expand-whens/bundle-init.fir | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'test/passes/expand-whens/bundle-init.fir')

diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 261ebf02..10da47cf 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -2,7 +2,9 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : { x : UInt, flip y : UInt}
+      input clk : Clock
+      input reset : UInt<1>
+      reg r : { x : UInt, flip y : UInt},clk,reset
       wire a : UInt
       wire b : UInt
       wire w : { x : UInt, flip y : UInt}
@@ -13,7 +15,7 @@ circuit top :
       w.y := a
       r.x := a
       r.y := b
-      on-reset r := w
+      onreset r := w
 
 ; CHECK: when UInt(1) : r$x := mux(reset, w$x, a)
 ; CHECK: when UInt(1) : r$y := b
-- 
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