diff options
| author | azidar | 2015-05-20 01:35:15 -0700 |
|---|---|---|
| committer | azidar | 2015-05-20 01:35:15 -0700 |
| commit | ed04a9040f20c5e04880a18ec036c1a641443c50 (patch) | |
| tree | cb9cd4db719484c0a8ea52054915841bc8e0eb14 /test/passes/expand-connect-indexed | |
| parent | 92e7da031a14df41ee0cab13a4a63b472fbdb5e1 (diff) | |
Added Pad pass to flo.stanza, which pads widths to make := and primops strict. Have not tested this
Diffstat (limited to 'test/passes/expand-connect-indexed')
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 7922c278..901ab4e6 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -7,23 +7,23 @@ circuit top : wire j : UInt wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a$0$x : UInt<32> - ; CHECK: wire a$0$y : UInt<32> - ; CHECK: wire a$1$x : UInt<32> - ; CHECK: wire a$1$y : UInt<32> + ; CHECK: wire a_0_x : UInt<32> + ; CHECK: wire a_0_y : UInt<32> + ; CHECK: wire a_1_x : UInt<32> + ; CHECK: wire a_1_y : UInt<32> accessor b = a[i] - ; CHECK: wire b$x : UInt<32> - ; CHECK: wire b$y : UInt<32> - ; CHECK: b$x := a$0$x - ; CHECK: node b$x#0 = i - ; CHECK: when eq(b$x#0, UInt(1)) : - ; CHECK: b$x := a$1$x - ; CHECK: node b$y#0 = i - ; CHECK: when eq(b$y#0, UInt(0)) : - ; CHECK: a$0$y := b$y - ; CHECK: when eq(b$y#0, UInt(1)) : - ; CHECK: a$1$y := b$y + ; CHECK: wire b_x : UInt<32> + ; CHECK: wire b_y : UInt<32> + ; CHECK: b_x := a_0_x + ; CHECK: node b_x__0 = i + ; CHECK: when eq(b_x__0, UInt(1)) : + ; CHECK: b_x := a_1_x + ; CHECK: node b_y__0 = i + ; CHECK: when eq(b_y__0, UInt(0)) : + ; CHECK: a_0_y := b_y + ; CHECK: when eq(b_y__0, UInt(1)) : + ; CHECK: a_1_y := b_y j := b.x ; CHECK: Finished Expand Indexed Connects |