Added tests, cleaned up repo

1 files changed, 16 insertions, 0 deletions

diff --git a/test/passes/expand-connect-indexed/init-vecs.fir b/test/passes/expand-connect-indexed/init-vecs.fir
new file mode 100644
index 00000000..7d64a117
--- /dev/null
+++ b/test/passes/expand-connect-indexed/init-vecs.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; XFAIL: *
+
+; CHECK: Expand Indexed Connects
+circuit top :
+   module top :
+      wire outs : UInt<32>[2][1]
+      outs[0][0] := UInt(1)
+      outs[0][1] := UInt(1)
+
+      write accessor out = outs[UInt(0)]
+      out[0] := UInt(1)
+
+; CHECK: Done!
+
+