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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-14 11:29:55 -0700
commit271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch)
tree8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/expand-connect-indexed/bundle-vecs.fir
parent0bfb3618b654a4082cc2780887b3ca32e374f455 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/expand-connect-indexed/bundle-vecs.fir')
-rw-r--r--test/passes/expand-connect-indexed/bundle-vecs.fir35
1 files changed, 20 insertions, 15 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index ea453ab1..38bd6fe5 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -4,27 +4,32 @@
circuit top :
module top :
wire i : UInt
+ i := UInt(1)
wire j : UInt
+ j := UInt(1)
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a$0$x : UInt<32>
- ; CHECK: wire a$0$y : UInt<32>
- ; CHECK: wire a$1$x : UInt<32>
- ; CHECK: wire a$1$y : UInt<32>
+ a[0].x := UInt(1)
+ a[0].y := UInt(1)
+ a[1].x := UInt(1)
+ a[1].y := UInt(1)
+ ; CHECK: wire a_0_x : UInt<32>
+ ; CHECK: wire a_0_y : UInt<32>
+ ; CHECK: wire a_1_x : UInt<32>
+ ; CHECK: wire a_1_y : UInt<32>
+
infer accessor b = a[i]
- ; CHECK: wire b$x : UInt<32>
- ; CHECK: wire b$y : UInt<32>
- ; CHECK: b$x := a$0$x
- ; CHECK: node i#0 = i
- ; CHECK: when eq(i#0, UInt(1)) :
- ; CHECK: b$x := a$1$x
- ; CHECK: node i#1 = i
- ; CHECK: when eq(i#1, UInt(0)) :
- ; CHECK: a$0$y := b$y
- ; CHECK: when eq(i#1, UInt(1)) :
- ; CHECK: a$1$y := b$y
+ ; CHECK: wire b_x : UInt<32>
+ ; CHECK: wire b_y : UInt<32>
+ ; CHECK: b_x := a_0_x
+ ; CHECK: node i!0 = i
+ ; CHECK: when eq(i!0, UInt(1)) : b_x := a_1_x
+ ; CHECK: node i!1 = i
+ ; CHECK: when eq(i!1, UInt(0)) : a_0_y := b_y
+ ; CHECK: when eq(i!1, UInt(1)) : a_1_y := b_y
j := b.x
+ b.y := UInt(1)
; CHECK: Finished Expand Indexed Connects