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authorAdam Izraelevitz2015-10-19 13:56:32 -0700
committerAdam Izraelevitz2015-10-19 13:56:32 -0700
commitf258c8394ebe7136e0eee7e1e342b5b593d1cc5d (patch)
tree5d000281afd7f217bee0c5c2030f3a17e079a3f0 /test/parser/bundle.fir
parent154c7d86a104264a3e3355d105f8e60926a10626 (diff)
parent80c055ce93c9d5988c6158c4a91c01633f8ebf22 (diff)
Merge pull request #47 from jackkoenig/master
Updated Scala FIRRTL with Testing and Infer-Types Pass
Diffstat (limited to 'test/parser/bundle.fir')
-rw-r--r--test/parser/bundle.fir43
1 files changed, 43 insertions, 0 deletions
diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir
new file mode 100644
index 00000000..c9600d10
--- /dev/null
+++ b/test/parser/bundle.fir
@@ -0,0 +1,43 @@
+; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s
+circuit top :
+ module top :
+ wire z : { x : UInt, flip y: SInt}
+ z.x := UInt(1)
+ z.y := SInt(1)
+ node x = z.x
+ node y = z.y
+ wire a : UInt<3>[10]
+ a[0] := UInt(1)
+ a[1] := UInt(1)
+ a[2] := UInt(1)
+ a[3] := UInt(1)
+ a[4] := UInt(1)
+ a[5] := UInt(1)
+ a[6] := UInt(1)
+ a[7] := UInt(1)
+ a[8] := UInt(1)
+ a[9] := UInt(1)
+ node b = a[2]
+ read accessor c = a[UInt(3)]
+
+; CHECK: circuit top :
+; CHECK: module top :
+; CHECK: wire z : { x : UInt, flip y : SInt}
+; CHECK: z.x := UInt("h1")
+; CHECK: z.y := SInt("h1")
+; CHECK: node x = z.x
+; CHECK: node y = z.y
+; CHECK: wire a : UInt<3>[10]
+; CHECK: a[0] := UInt("h1")
+; CHECK: a[1] := UInt("h1")
+; CHECK: a[2] := UInt("h1")
+; CHECK: a[3] := UInt("h1")
+; CHECK: a[4] := UInt("h1")
+; CHECK: a[5] := UInt("h1")
+; CHECK: a[6] := UInt("h1")
+; CHECK: a[7] := UInt("h1")
+; CHECK: a[8] := UInt("h1")
+; CHECK: a[9] := UInt("h1")
+; CHECK: node b = a[2]
+; CHECK: read accessor c = a[UInt("h3")]
+