Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 11 insertions, 11 deletions

diff --git a/test/integration/MemTester.fir b/test/integration/MemTester.fir
index 451ec5d3..f3d04be4 100644
--- a/test/integration/MemTester.fir
+++ b/test/integration/MemTester.fir
@@ -1,17 +1,17 @@
 
 circuit MemTester :
   module ReadWrite :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg n : UInt<32>, clk with :
+    reg n : UInt<32>, clock with :
       reset => (reset, UInt(0))
 
-    reg wmode : UInt<1>, clk with : 
+    reg wmode : UInt<1>, clock with :
       reset => (reset, UInt(1))
     wmode <= not(wmode)
 
-    reg addr : UInt<5>, clk with :
+    reg addr : UInt<5>, clock with :
       reset => (reset, UInt(0))
 
     when eq(wmode, UInt(0)) :
@@ -25,7 +25,7 @@ circuit MemTester :
       write-latency => 1
       readwriter => rw
       read-under-write => undefined
-    m.rw.clk <= clk
+    m.rw.clk <= clock
     m.rw.addr <= addr
     m.rw.wmode <= wmode
     m.rw.wdata <= n
@@ -35,21 +35,21 @@ circuit MemTester :
     when not(reset) :
       when eq(wmode, UInt(0)) :
         when neq(m.rw.rdata, n) :
-          printf(clk, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
-          stop(clk, UInt(1), 1)
+          printf(clock, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
+          stop(clock, UInt(1), 1)
 
   module MemTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg count : UInt<32>, clk with :
+    reg count : UInt<32>, clock with :
       reset => (reset, UInt(100))
     count <= tail(sub(count, UInt(1)), 1)
 
     inst rwMod of ReadWrite
-    rwMod.clk <= clk
+    rwMod.clock <= clock
     rwMod.reset <= reset
 
     when eq(count, UInt(0)) :
-      stop(clk, UInt(1), 0)
+      stop(clock, UInt(1), 0)