diff options
| author | azidar | 2015-07-31 16:05:53 -0700 |
|---|---|---|
| committer | azidar | 2015-07-31 16:05:53 -0700 |
| commit | d5cc3210aabf7b4d69e2f3c5ed45c9c097c3ebdf (patch) | |
| tree | f16aa7305b4ce27d38f679332d7ad37e6f6fef3a /test/features/TwoClocks.fir | |
| parent | 2440b824c68e4604d174e92e26af2c3eca1ec171 (diff) | |
Updated tests to pipe from stderr to stdout
Diffstat (limited to 'test/features/TwoClocks.fir')
| -rw-r--r-- | test/features/TwoClocks.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir index cbbb01f1..9665c153 100644 --- a/test/features/TwoClocks.fir +++ b/test/features/TwoClocks.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s circuit Top : module Top : input clk1 : Clock |