diff options
| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/features/IsInvalid.fir | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/features/IsInvalid.fir')
| -rw-r--r-- | test/features/IsInvalid.fir | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir index cf898fe9..dc7c56b4 100644 --- a/test/features/IsInvalid.fir +++ b/test/features/IsInvalid.fir @@ -12,9 +12,10 @@ circuit Top : write-latency => 1 reader => r writer => w - read-writer => rw + readwriter => rw wire x : { w : UInt<42>, x : UInt<20>} - reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x + reg c : { w : UInt<42>, x : UInt<20>},clk with : + reset => (reset,x) inst other of Other clk is invalid @@ -52,7 +53,7 @@ circuit Top : ;CHECK: m.w.addr is invalid ;CHECK: m.w.en is invalid ;CHECK: m.w.clk is invalid -;CHECK: m.rw.rmode is invalid +;CHECK: m.rw.wmode is invalid ;CHECK: m.rw.data[0] is invalid ;CHECK: m.rw.data[1] is invalid ;CHECK: m.rw.data[2] is invalid |