From 5ab30c681558d2a26000696e518ee5b28deb1303 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:18:34 -0800
Subject: Updated all tests to pass

---
 test/features/IsInvalid.fir | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'test/features/IsInvalid.fir')

diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
index cf898fe9..f6766bf2 100644
--- a/test/features/IsInvalid.fir
+++ b/test/features/IsInvalid.fir
@@ -12,9 +12,10 @@ circuit Top :
        write-latency => 1
        reader => r
        writer => w
-       read-writer => rw
+       readwriter => rw
     wire x : { w : UInt<42>, x : UInt<20>}
-    reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x
+    reg c : { w : UInt<42>, x : UInt<20>},clk with :
+       reset => (reset,x)
     inst other of Other
    
     clk is invalid
-- 
cgit v1.2.3


From cfedffd1fc7d5846e9f633bf13ea194b8ab2293d Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 15:59:48 -0800
Subject: Changed rmode to wmode

---
 test/features/IsInvalid.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/features/IsInvalid.fir')

diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
index f6766bf2..dc7c56b4 100644
--- a/test/features/IsInvalid.fir
+++ b/test/features/IsInvalid.fir
@@ -53,7 +53,7 @@ circuit Top :
 ;CHECK: m.w.addr is invalid
 ;CHECK: m.w.en is invalid
 ;CHECK: m.w.clk is invalid
-;CHECK: m.rw.rmode is invalid
+;CHECK: m.rw.wmode is invalid
 ;CHECK: m.rw.data[0] is invalid
 ;CHECK: m.rw.data[1] is invalid
 ;CHECK: m.rw.data[2] is invalid
-- 
cgit v1.2.3