diff options
| author | azidar | 2015-07-31 16:05:53 -0700 |
|---|---|---|
| committer | azidar | 2015-07-31 16:05:53 -0700 |
| commit | d5cc3210aabf7b4d69e2f3c5ed45c9c097c3ebdf (patch) | |
| tree | f16aa7305b4ce27d38f679332d7ad37e6f6fef3a /test/features/InitializeVec.fir | |
| parent | 2440b824c68e4604d174e92e26af2c3eca1ec171 (diff) | |
Updated tests to pipe from stderr to stdout
Diffstat (limited to 'test/features/InitializeVec.fir')
| -rw-r--r-- | test/features/InitializeVec.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir index 30c59fb9..0d49cf2a 100644 --- a/test/features/InitializeVec.fir +++ b/test/features/InitializeVec.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! circuit Tst : module Tst : - output in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} + input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] in.ready := UInt<1>(1) |