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| author | Jack | 2016-02-23 00:57:09 -0800 |
|---|---|---|
| committer | Jack | 2016-02-23 00:57:09 -0800 |
| commit | c48c691e94afe4919c20fa588a9897316c572447 (patch) | |
| tree | 4e2e09a72a7134c4e7cda7830af837342488fa39 /test/errors/parser | |
| parent | 6ec6edea9a60f8aab80ee287547160ffaf73aaf7 (diff) | |
Add rocket regression, just runs rocket.fir through Verilog compiler and compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
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