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| author | Andrew Waterman | 2016-06-23 12:14:57 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-06-23 12:14:57 -0700 |
| commit | 85dc973ecc3042370f218b77dfa0990fde6c2e0f (patch) | |
| tree | 8045ed053fb05af526c2cfbb98693176bb90ab45 /test/errors/parser/InstanceNotRef.fir | |
| parent | 860b04eff7758c3efae09fb0b5b908abad3b4593 (diff) | |
Emit more useful code for stop
- Based upon stop value, use $fatal instead of $finish. This causes
the Verilog simulator to signal an error to the OS as appropriate.
- Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS).
Diffstat (limited to 'test/errors/parser/InstanceNotRef.fir')
0 files changed, 0 insertions, 0 deletions