diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/high-form/SpecialChars.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/errors/high-form/SpecialChars.fir')
| -rw-r--r-- | test/errors/high-form/SpecialChars.fir | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir index 99df9143..85911c06 100644 --- a/test/errors/high-form/SpecialChars.fir +++ b/test/errors/high-form/SpecialChars.fir @@ -4,32 +4,32 @@ circuit Top : module Top : wire x : UInt<1> - x := UInt(1) + x <= UInt(1) wire x~y : UInt<2> - x~y := UInt(1) + x~y <= UInt(1) wire x!y : UInt<2> - x!y := UInt(1) + x!y <= UInt(1) wire x@y : UInt<2> - x@y := UInt(1) + x@y <= UInt(1) wire x#y : UInt<2> - x#y := UInt(1) + x#y <= UInt(1) wire x%y : UInt<2> - x%y := UInt(1) + x%y <= UInt(1) wire x^y : UInt<2> - x^y := UInt(1) + x^y <= UInt(1) wire x*y : UInt<2> - x*y := UInt(1) + x*y <= UInt(1) wire x-y : UInt<2> - x-y := UInt(1) + x-y <= UInt(1) wire x_y : UInt<2> - x_y := UInt(1) + x_y <= UInt(1) wire x+y : UInt<2> - x+y := UInt(1) + x+y <= UInt(1) wire x=y : UInt<2> - x=y := UInt(1) + x=y <= UInt(1) wire x?y : UInt<2> - x?y := UInt(1) + x?y <= UInt(1) wire x/y : UInt<2> - x/y := UInt(1) + x/y <= UInt(1) |