From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/high-form/SpecialChars.fir | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'test/errors/high-form/SpecialChars.fir')

diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir
index 99df9143..85911c06 100644
--- a/test/errors/high-form/SpecialChars.fir
+++ b/test/errors/high-form/SpecialChars.fir
@@ -4,32 +4,32 @@
 circuit Top :
   module Top :
     wire x : UInt<1>
-    x := UInt(1)
+    x <= UInt(1)
     wire x~y : UInt<2>
-    x~y := UInt(1)
+    x~y <= UInt(1)
     wire x!y : UInt<2>
-    x!y := UInt(1)
+    x!y <= UInt(1)
     wire x@y : UInt<2>
-    x@y := UInt(1)
+    x@y <= UInt(1)
     wire x#y : UInt<2>
-    x#y := UInt(1)
+    x#y <= UInt(1)
     wire x%y : UInt<2>
-    x%y := UInt(1)
+    x%y <= UInt(1)
     wire x^y : UInt<2>
-    x^y := UInt(1)
+    x^y <= UInt(1)
     wire x*y : UInt<2>
-    x*y := UInt(1)
+    x*y <= UInt(1)
     wire x-y : UInt<2>
-    x-y := UInt(1)
+    x-y <= UInt(1)
     wire x_y : UInt<2>
-    x_y := UInt(1)
+    x_y <= UInt(1)
     wire x+y : UInt<2>
-    x+y := UInt(1)
+    x+y <= UInt(1)
     wire x=y : UInt<2>
-    x=y := UInt(1)
+    x=y <= UInt(1)
     wire x?y : UInt<2>
-    x?y := UInt(1)
+    x?y <= UInt(1)
     wire x/y : UInt<2>
-    x/y := UInt(1)
+    x/y <= UInt(1)
 
 
-- 
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