New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 10 insertions, 10 deletions

diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 830e8156..1becd104 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -9,18 +9,18 @@ circuit BTB :
     input in : {x : UInt<1>, flip y : {flip z : UInt<1>}}
     output out : {x : UInt<1>, flip y : {flip z : UInt<1>}}
 
-    in <> out
-    out.y <> in.y
-    out.y.z <> in.y.z
+    in <- out
+    out.y <- in.y
+    out.y.z <- in.y.z
     
     wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}}
-    w <> in
-    in.y <> w.y
-    in.y.z <> w.y.z
+    w <- in
+    in.y <- w.y
+    in.y.z <- w.y.z
 
-    w.x := addw(in.x,in.y.z)
+    w.x <= addw(in.x,in.y.z)
 
-    out <> in
-    in.y <> out.y
-    in.y.z <> out.y.z
+    out <- in
+    in.y <- out.y
+    in.y.z <- out.y.z