From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/gender/BulkWrong.fir | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'test/errors/gender/BulkWrong.fir')

diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 830e8156..1becd104 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -9,18 +9,18 @@ circuit BTB :
     input in : {x : UInt<1>, flip y : {flip z : UInt<1>}}
     output out : {x : UInt<1>, flip y : {flip z : UInt<1>}}
 
-    in <> out
-    out.y <> in.y
-    out.y.z <> in.y.z
+    in <- out
+    out.y <- in.y
+    out.y.z <- in.y.z
     
     wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}}
-    w <> in
-    in.y <> w.y
-    in.y.z <> w.y.z
+    w <- in
+    in.y <- w.y
+    in.y.z <- w.y.z
 
-    w.x := addw(in.x,in.y.z)
+    w.x <= addw(in.x,in.y.z)
 
-    out <> in
-    in.y <> out.y
-    in.y.z <> out.y.z
+    out <- in
+    in.y <- out.y
+    in.y.z <- out.y.z
 
-- 
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