new chisel3 tests

1 files changed, 19 insertions, 0 deletions

diff --git a/test/chisel3/VecShiftRegister.fir b/test/chisel3/VecShiftRegister.fir
new file mode 100644
index 00000000..86f20796
--- /dev/null
+++ b/test/chisel3/VecShiftRegister.fir
@@ -0,0 +1,19 @@
+circuit VecShiftRegister : 
+  module VecShiftRegister : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when load : 
+      delays.0 := ins.0
+      delays.1 := ins.1
+      delays.2 := ins.2
+      delays.3 := ins.3
+     else : when shift : 
+        delays.0 := ins.0
+        delays.1 := delays.0
+        delays.2 := delays.1
+        delays.3 := delays.2
+    out := delays.3
\ No newline at end of file