diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-07 10:13:29 -0700 |
| commit | df4bae5c7a95d3a56f95d86212f083b7ba121da7 (patch) | |
| tree | af46f090557734528d9d29fcf499d73024c575ac /test/chisel3/Stack.fir | |
| parent | c8d1fc06443e81374b1af95e17e3ecbecf863700 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/chisel3/Stack.fir')
| -rw-r--r-- | test/chisel3/Stack.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir index caa70da5..52c9b437 100644 --- a/test/chisel3/Stack.fir +++ b/test/chisel3/Stack.fir @@ -18,7 +18,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = bit-and(push, T_30) when T_31 : - accessor T_32 = stack_mem[sp] + infer accessor T_32 = stack_mem[sp] T_32 := dataIn node T_33 = add-wrap(sp, UInt<1>(1)) sp := T_33 @@ -31,6 +31,6 @@ circuit Stack : node T_37 = gt(sp, UInt<1>(0)) when T_37 : node T_38 = sub-wrap(sp, UInt<1>(1)) - accessor T_39 = stack_mem[T_38] + infer accessor T_39 = stack_mem[T_38] out := T_39 dataOut := out |