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authorjackbackrack2015-04-20 15:21:30 -0700
committerjackbackrack2015-04-20 15:21:30 -0700
commit6204b6d44aef2f47a8009ad06dfd4e09ce7ce950 (patch)
tree8795de870f20086b0615f7c402c234b79e6a71a0 /test/chisel3/Mul.fir
parent5298af3dffcd0985922a2a8317fa6a67e192a9c0 (diff)
parent7617e33993abf9f6be357e0261755a4736c2e085 (diff)
merge
Diffstat (limited to 'test/chisel3/Mul.fir')
-rw-r--r--test/chisel3/Mul.fir75
1 files changed, 38 insertions, 37 deletions
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index e41537e3..4f954465 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -1,44 +1,45 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
circuit Mul :
module Mul :
input y : UInt(2)
input x : UInt(2)
output z : UInt(4)
- node T_44 : UInt(4) = UInt(0, 4)
- node T_45 : UInt(4) = UInt(0, 4)
- node T_46 : UInt(4) = UInt(0, 4)
- node T_47 : UInt(4) = UInt(0, 4)
- node T_48 : UInt(4) = UInt(0, 4)
- node T_49 : UInt(4) = UInt(1, 4)
- node T_50 : UInt(4) = UInt(2, 4)
- node T_51 : UInt(4) = UInt(3, 4)
- node T_52 : UInt(4) = UInt(0, 4)
- node T_53 : UInt(4) = UInt(2, 4)
- node T_54 : UInt(4) = UInt(4, 4)
- node T_55 : UInt(4) = UInt(6, 4)
- node T_56 : UInt(4) = UInt(0, 4)
- node T_57 : UInt(4) = UInt(3, 4)
- node T_58 : UInt(4) = UInt(6, 4)
- node T_59 : UInt(4) = UInt(9, 4)
+ node T_43 = UInt(0, 4)
+ node T_44 = UInt(0, 4)
+ node T_45 = UInt(0, 4)
+ node T_46 = UInt(0, 4)
+ node T_47 = UInt(0, 4)
+ node T_48 = UInt(1, 4)
+ node T_49 = UInt(2, 4)
+ node T_50 = UInt(3, 4)
+ node T_51 = UInt(0, 4)
+ node T_52 = UInt(2, 4)
+ node T_53 = UInt(4, 4)
+ node T_54 = UInt(6, 4)
+ node T_55 = UInt(0, 4)
+ node T_56 = UInt(3, 4)
+ node T_57 = UInt(6, 4)
+ node T_58 = UInt(9, 4)
wire tbl : UInt(4)[16]
- tbl.0 := T_44
- tbl.1 := T_45
- tbl.2 := T_46
- tbl.3 := T_47
- tbl.4 := T_48
- tbl.5 := T_49
- tbl.6 := T_50
- tbl.7 := T_51
- tbl.8 := T_52
- tbl.9 := T_53
- tbl.10 := T_54
- tbl.11 := T_55
- tbl.12 := T_56
- tbl.13 := T_57
- tbl.14 := T_58
- tbl.15 := T_59
- node T_60 : UInt(2) = UInt(2, 2)
- node T_61 : UInt(2) = shift-left(x, T_60)
- node T_62 : UInt(2) = bit-or(T_61, y)
- accessor T_63 = tbl[T_62]
- z := T_63
+ tbl.0 := T_43
+ tbl.1 := T_44
+ tbl.2 := T_45
+ tbl.3 := T_46
+ tbl.4 := T_47
+ tbl.5 := T_48
+ tbl.6 := T_49
+ tbl.7 := T_50
+ tbl.8 := T_51
+ tbl.9 := T_52
+ tbl.10 := T_53
+ tbl.11 := T_54
+ tbl.12 := T_55
+ tbl.13 := T_56
+ tbl.14 := T_57
+ tbl.15 := T_58
+ node T_60 = shl(x, 2)
+ node T_61 = bit-or(T_60, y)
+ accessor T_62 = tbl[T_61]
+ z := T_62