aboutsummaryrefslogtreecommitdiff
path: root/test/chisel3/LFSR16.fir
diff options
context:
space:
mode:
authorjackbackrack2015-04-28 18:25:40 -0700
committerjackbackrack2015-04-28 18:25:40 -0700
commit4b64107635c702352721a8fbb6ee71a455b9da54 (patch)
treee66da971c5ac7e2866db9371522d07d10b115053 /test/chisel3/LFSR16.fir
parent2a4f374b19e10a1571fbd2a23b30e92c9179defd (diff)
parentc46608d92bd493fa33c3c5122341c716ca75ecb0 (diff)
merge
Diffstat (limited to 'test/chisel3/LFSR16.fir')
-rw-r--r--test/chisel3/LFSR16.fir10
1 files changed, 5 insertions, 5 deletions
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index a8857882..b635e4bf 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -3,12 +3,12 @@
circuit LFSR16 :
module LFSR16 :
- output out : UInt(16)
- input inc : UInt(1)
+ output out : UInt<16>
+ input inc : UInt<1>
- node T_16 = UInt(1, 16)
- reg res : UInt(16)
- res.init := T_16
+ node T_16 = UInt<16>(1)
+ reg res : UInt<16>
+ on-reset res := T_16
when inc :
node T_17 = bit(res, 0)
node T_18 = bit(res, 2)