From 1644ed195522cd7343aaaa047e6669529907de9f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 28 Apr 2015 17:32:19 -0700
Subject: Instances are now male. Reworked lowering pass to be sane.
 chisel3/ModuleVec.fir doesn't work because incorrecly generated?

---
 test/chisel3/LFSR16.fir | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'test/chisel3/LFSR16.fir')

diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index a8857882..b635e4bf 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -3,12 +3,12 @@
 
 circuit LFSR16 : 
   module LFSR16 : 
-    output out : UInt(16)
-    input inc : UInt(1)
+    output out : UInt<16>
+    input inc : UInt<1>
     
-    node T_16 = UInt(1, 16)
-    reg res : UInt(16)
-    res.init := T_16
+    node T_16 = UInt<16>(1)
+    reg res : UInt<16>
+    on-reset res := T_16
     when inc : 
       node T_17 = bit(res, 0)
       node T_18 = bit(res, 2)
-- 
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