diff options
| author | jackbackrack | 2015-04-20 15:21:30 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-04-20 15:21:30 -0700 |
| commit | 6204b6d44aef2f47a8009ad06dfd4e09ce7ce950 (patch) | |
| tree | 8795de870f20086b0615f7c402c234b79e6a71a0 /test/chisel3/EnableShiftRegister.fir | |
| parent | 5298af3dffcd0985922a2a8317fa6a67e192a9c0 (diff) | |
| parent | 7617e33993abf9f6be357e0261755a4736c2e085 (diff) | |
merge
Diffstat (limited to 'test/chisel3/EnableShiftRegister.fir')
| -rw-r--r-- | test/chisel3/EnableShiftRegister.fir | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir deleted file mode 100644 index 732e1dbc..00000000 --- a/test/chisel3/EnableShiftRegister.fir +++ /dev/null @@ -1,27 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit EnableShiftRegister : - module EnableShiftRegister : - input in : UInt(4) - output out : UInt(4) - input shift : UInt(1) - - node T_14 = UInt(0, 4) - reg r0 : UInt(4) - r0.init := T_14 - node T_15 = UInt(0, 4) - reg r1 : UInt(4) - r1.init := T_15 - node T_16 = UInt(0, 4) - reg r2 : UInt(4) - r2.init := T_16 - node T_17 = UInt(0, 4) - reg r3 : UInt(4) - r3.init := T_17 - when shift : - r0 := in - r1 := r0 - r2 := r1 - r3 := r2 - out := r3 -;CHECK: Finished To Flo |