diff options
| author | azidar | 2016-01-16 14:13:28 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:19 -0800 |
| commit | cd7587547733ab879719344ba29ff354dc5b6faa (patch) | |
| tree | 416bdfc8aec1c90ee751eb59fb62a24d660b8794 /test/chirrtl | |
| parent | 480f26999b734271d5a730cc288644d5bef1b8d9 (diff) | |
Fixed a test
Diffstat (limited to 'test/chirrtl')
| -rw-r--r-- | test/chirrtl/wacc-wdc.fir | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir index 71b86d70..32b61c3b 100644 --- a/test/chirrtl/wacc-wdc.fir +++ b/test/chirrtl/wacc-wdc.fir @@ -6,19 +6,32 @@ circuit top : cmem m : UInt<4>[10] p <= UInt(1) when p : - write mport a = m[UInt(3)],clk + write mport a = m[UInt(3)],clk,UInt(1) a <= UInt(2) -; CHECK: Expand Whens +; CHECK: To FIRRTL -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: cmem m : UInt<4>[10], clk -; CHECK: write accessor a = m[UInt("h3")] -; CHECK: p <= UInt("h1") -; CHECK: when p : a <= UInt("h2") +; CHECK: mem m : +; CHECK: data-type: UInt<4> +; CHECK: depth: 10 +; CHECK: write-latency: 1 +; CHECK: read-latency: 0 +; CHECK: writer: a +; CHECK: poison GEN : UInt<4> +; CHECK: poison GEN_1 : UInt<4> +; CHECK: m.a.addr <= GEN +; CHECK: m.a.clk <= clk +; CHECK: m.a.en <= UInt("h0") +; CHECK: m.a.data <= GEN_1 +; CHECK: m.a.mask <= UInt("h0") +; CHECK: p <= UInt("h1") +; CHECK: when p : +; CHECK: m.a.addr <= UInt("h3") +; CHECK: m.a.en <= UInt("h1") +; CHECK: m.a.mask <= UInt("h1") +; CHECK: m.a.data <= UInt("h2") -; CHECK: Finished Expand Whens +; CHECK: Finished To FIRRTL +; CHECK: Done! |